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tinypower tm a/d flash mcu with lcd & eeprom HT67F488 ht67f489 revision: v1.60 date: ? ove ?? e ? ??? ? 016 ? ove ?? e ? ??? ? 016
rev. 1.60 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom table of contents eates cpu featu ? es ......................................................................................................................... 6 pe ? iphe ? al featu ? es ................................................................................................................. 6 gene?al desc?iption ......................................................................................... 7 selection ta?le ................................................................................................. 8 block diag?a? .................................................................................................. 8 pin assign?ent ........... ..................................................................................... 9 pin desc?iption .......... .................................................................................... 10 a?solute maxi?u? ratings .......................................................................... 13 d.c. cha?acte?istics ....................................................................................... 13 a.c. cha?acte?istics ....................................................................................... 15 a/d conve?te? elect?ical cha?acte?istics ........... .......................................... 16 lvd & lvr elect?ical cha?acte?istics .......................................................... 16 powe? on reset cha?acte?istics ................................................................... 17 syste? a?chitectu?e ...................................................................................... 18 clocking and pipelining ......................................................................................................... 18 p ? og ? a ? counte ? ................................................................................................................... 19 stack ..................................................................................................................................... ? 0 a ? ith ? etic and logic unit C alu ........................................................................................... ? 0 flash p?og?a? me?o?y ................................................................................. ?1 st ? uctu ? e ................................................................................................................................ ? 1 special vecto ? s ..................................................................................................................... ? 1 look-up ta ? le ............. ........................................................................................................... ?? ta ? le p ? og ? a ? exa ? ple ........................................................................................................ ?? in ci ? cuit p ? og ? a ?? ing C icp ............................................................................................... ? 3 on-chip de ? ug suppo ? t C ocds ......................................................................................... ? 4 ram data me?o?y ......................................................................................... ?5 st ? uctu ? e ................................................................................................................................ ? 5 data me ? o ? y add ? essing ...................................................................................................... ? 6 gene ? al pu ? pose data me ? o ? y ........................................................................................... ? 6 special pu ? pose data me ? o ? y ............................................................................................ ? 6 special function registe? desc?iption ........................................................ ?8 indi ? ect add ? essing registe ? C iar0 ? iar1 ? iar ? ............. .................................................... ? 8 me ? o ? y pointe ? s C mp0 ? mp1l ? mp1h ? mp ? l ? mp ? h ......................................................... ? 8 accu ? ulato ? C acc ............................................................................................................... 30 p ? og ? a ? counte ? low registe ? C pcl ................................................................................. 30 look-up ta ? le registe ? s C tblp ? tbhp ? tblh .................................................................... 31 status registe ? C status ................................................................................................... 31
rev. 1.60 3 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom eeprom data memory ........... ....................................................................... 33 eeprom data me ? o ? y st ? uctu ? e ........................................................................................ 33 eeprom registe ? s ............ .................................................................................................. 33 reading data f ? o ? the eeprom ......................................................................................... 35 w ? iting data to the eeprom ................................................................................................ 35 w ? ite p ? otection ..................................................................................................................... 35 eeprom inte ?? upt ............. ................................................................................................... 35 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 36 p ? og ? a ?? ing exa ? ples ........................................................................................................ 36 oscillators .......... ............................................................................................ 37 oscillato ? ove ? view ............. ................................................................................................. 37 system clock confgurations ............................................................................................... 37 exte ? nal c ? ystal/ce ? a ? ic oscillato ? C hxt ........................................................................... 38 inte ? nal rc oscillato ? C hirc ............. ................................................................................. 38 exte ? nal 3 ? .768khz c ? ystal oscillato ? C lxt ............. ........................................................... 39 lxt oscillato ? low powe ? function ..................................................................................... 40 inte ? nal 3 ? khz oscillato ? C lirc .......................................................................................... 40 operating modes and system clocks ........................................................ 41 syste ? clocks ..................................................................................................................... 41 syste ? ope ? ation modes ..................................................................................................... 4 ? cont ? ol registe ? .................................................................................................................... 43 ope ? ating mode switching ................................................................................................... 45 stand ? y cu ?? ent conside ? ations .......................................................................................... 49 wake-up ............................................................................................................................... 49 watchdog timer ........... .................................................................................. 50 watchdog ti ? e ? clock sou ? ce .............................................................................................. 50 watchdog ti ? e ? cont ? ol registe ? ............. ............................................................................ 50 watchdog ti ? e ? ope ? ation ................................................................................................... 51 reset and initialisation .................................................................................. 52 reset functions ............. ...................................................................................................... 5 ? reset initial conditions ........................................................................................................ 55 input/output ports ........................................................................................ 58 pull-high resisto ? s ................................................................................................................ 59 po ? t a wake-up ............. ........................................................................................................ 59 i/o po ? t cont ? ol registe ? s ..................................................................................................... 59 pin-sha ? ed functions ............. ............................................................................................... 59 i/o pin st ? uctu ? es .................................................................................................................. 60 p ? og ? a ?? ing conside ? ations ............. .................................................................................. 61 timer modules C tm .......... ............................................................................ 62 int ? oduction ........................................................................................................................... 6 ? tm ope ? ation ............. ........................................................................................................... 6 ? tm clock sou ? ce ............. ...................................................................................................... 63 tm inte ?? upts ......................................................................................................................... 63
rev. 1.60 4 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tm exte ? nal pins .................................................................................................................. 63 tm input/output pin cont ? ol registe ? s ............. .................................................................... 63 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 65 periodic type tm C ptm ................................................................................ 66 pe ? iodic tm ope ? ation ............. ............................................................................................. 66 pe ? iodic type tm registe ? desc ? iption ................................................................................. 67 pe ? iodic type tm ope ? ating modes ...................................................................................... 7 ? compact type tm C ctm .............................................................................. 81 co ? pact tm ope ? ation ........................................................................................................ 81 co ? pact type tm registe ? desc ? iption ................................................................................ 8 ? co ? pact type tm ope ? ating modes .................................................................................... 86 analog to digital converter C adc ........... .................................................... 92 a/d ove ? view ............. ........................................................................................................... 9 ? a/d conve ? te ? registe ? desc ? iption ...................................................................................... 9 ? a/d conve ? te ? data registe ? s C adrl ? adrh ..................................................................... 93 a/d conve ? te ? cont ? ol registe ? s C adcr0 ? adcr1 ? acerl ? acerh ................................ 93 a/d ope ? ation ...................................................................................................................... 97 a/d input pins ............. .......................................................................................................... 98 su ?? a ? y of a/d conve ? sion steps ............. ......................................................................... 99 p ? og ? a ?? ing conside ? ations ............. ................................................................................. 100 a/d t ? ansfe ? function ............. ............................................................................................ 100 a/d p ? og ? a ?? ing exa ? ple ................................................................................................. 101 lcd display memory ................................................................................... 103 lcd d ? ive ? output ............................................................................................................... 103 lcd cont ? ol registe ? .......................................................................................................... 104 lcd wavefo ?? .................................................................................................................... 108 led driver ..................................................................................................... 111 led d ? ive ? ope ? ation ........................................................................................................... 111 led d ? ive ? registe ? ............................................................................................................. 111 uart interface .............................................................................................. 112 uart exte ? nal pin inte ? facing ............................................................................................. 113 uart data t ? ansfe ? sche ? e ............................................................................................... 113 uart status and cont ? ol registe ? s ..................................................................................... 113 baud rate gene ? ato ? ........................................................................................................... 119 uart setup and cont ? ol ..................................................................................................... 1 ? 0 uart t ? ans ? itte ? ................................................................................................................ 1 ?? uart receive ? ............. ...................................................................................................... 1 ? 3 managing receive ? e ?? o ? s .................................................................................................. 1 ? 5 uart module inte ?? upt st ? uctu ? e ........................................................................................ 1 ? 6 add ? ess detect mode .......................................................................................................... 1 ? 7 uart module powe ? down and wake-up ............. ............................................................. 1 ? 7
rev. 1.60 5 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom interrupts ...................................................................................................... 129 inte ?? upt registe ? s ............................................................................................................... 1 ? 9 inte ?? upt ope ? ation .............................................................................................................. 137 exte ? nal inte ?? upt ............. .................................................................................................... 139 multi-function inte ?? upt ........................................................................................................ 139 a/d conve ? te ? inte ?? upt ....................................................................................................... 139 uart inte ?? upt ............. ....................................................................................................... 140 ti ? e base inte ?? upt ............................................................................................................. 140 eeprom inte ?? upt ............. ................................................................................................. 141 lvd inte ?? upt ....................................................................................................................... 14 ? tm inte ?? upts ...................................................................................................................... 14 ? inte ?? upt wake-up function ................................................................................................. 14 ? p ? og ? a ?? ing conside ? ations ............. ................................................................................. 143 low voltage detector C lvd .......... ............................................................. 144 lvd registe ? ............. .......................................................................................................... 144 lvd ope ? ation ..................................................................................................................... 145 confguration options ................................................................................. 146 application circuits ........... .......................................................................... 146 instruction set .............................................................................................. 147 int ? oduction ......................................................................................................................... 147 inst ? uction ti ? ing ................................................................................................................ 147 moving and t ? ansfe ?? ing data ............................................................................................. 147 a ? ith ? etic ope ? ations .......................................................................................................... 147 logical and rotate ope ? ation ............................................................................................. 148 b ? anches and cont ? ol t ? ansfe ? ........................................................................................... 148 bit ope ? ations ..................................................................................................................... 148 ta ? le read ope ? ations ....................................................................................................... 148 othe ? ope ? ations ............. .................................................................................................... 148 instruction set summary .......... .................................................................. 149 ta ? le conventions ............................................................................................................... 149 extended inst ? uction set ............. ........................................................................................ 151 instruction defnition ................................................................................... 153 ([whqghg,qvwuxfwlrqhqlwlrq ........................................................................................... 16 ? package information ................................................................................... 169 44-pin lqfp (10 ?? 10 ?? ) (fp ? .0 ?? ) outline di ? ensions ........................................... 170
rev. 1.60 6 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom features cpu features ? operating v oltage f sys = 4mhz: 2.2v~5.5v f sys = 8mhz: 2.2v~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 16mhz: 4.5v~5.5v ? power down and wake-up functions to reduce power consumption ? oscillators internal rc C hirc external crystal - hxt internal 32khz rc C lirc external 32.768khz crystal C lxt ? fully integrated internal 8mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in 1~3 instruction cycles ? bit manipulation instruction ? 16-bit t able read function ? 115 powerful instructions ? support dual words instructions for ram access ? 8-level subroutine nesting peripheral features ? flash program memory: 4k16 ~ 8k16 ? ram data memory: 2568 ? true eeprom memory: 648 (only for ht67f489) ? watchdog t imer function ? 42 bidirectional i/o lines inlcude lcd/led driving output ? 4 pin-shared external interrupts ? multiple t imer modules for time measure, input capture, compare matc h output, pwm output or single pulse output functions ? dual t ime-base functions for generation of fxed time interrupt signals ? 10-channel 12-bit resolution a/d converter ? lcd display 20seg 4com & 20seg 8com 1/3 or 1/4 bias ? led display: 8seg 8com ? fully-duplex universal asynchronous receiver and t ransmitter interface -- uart ? low v oltage reset function ? low v oltage detect function ? package type: 44-pin lqfp
rev. 1.60 7 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom general description the HT67F488/ht67f489 series of devices are flash memory a/d type 8-bit high performance risc architecture microcontrollers, designed especially for applications that interface directly to analog signals, such as those from sensors. of fering users the convenience of flash memory multi- programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory (only for ht67f489) for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter function. multiple and extremely fexible t imer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal w atchdog t imer, low v oltage reset and low v oltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a f ull c hoice o f hi rc, hxt , l xt a nd l irc o scillator f unctions a re p rovided i ncluding a f ully integrated system oscillator which requires no external components for its implementation. the ability t o opera te a nd swi tch dyna mically be tween a ra nge of opera ting m odes usi ng di fferent clock s ources gives us ers the ability to optimis e microcontroller operation and minimize pow er consumption. the uar t module is contained in these devices. it can support the applications such as data communication networks between microcontrollers, low-cost data links between pcs and peripheral devices, portable and battery operated device communication, etc. the inclu sion of both lcd and led driver functions allows for easy and cost ef fective solutions in applications that require interface to these display types. the inclusion of fexible i/o programming features, t ime-base functions along with many other features enhance the versatility of these devices to suit a wide range of a/d application possibilities such as sensor s ignal process ing, char gers, motor driving, indus trial control, cons umer products , subsystem controllers, etc.
rev. 1.60 8 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom selection table most features are common to all devices, the main feature distinguishing them are memory capacity and whether eeprom or not. the following table summarises the main features of each device. part no. program memory data memory data eeprom i/o ext. interrupt a/d lcd driver HT67F488 4k16 ? 568 4 ? 4 1 ? - ? it10 ? 04 ? ? 08 ht67f489 8k16 ? 568 648 4 ? 4 1 ? - ? it10 ? 04 ? ? 08 part no. led driver timer module time base uart stack package HT67F488 8x8 10- ? it ctm3 10- ? it ptm1 ? 8 44lqfp ht67f489 8x8 10- ? it ctm3 10- ? it ptm1 ? 8 44lqfp block diagram
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? ? - ? ? ? ? ?? ? ? ? ? - ? ? ? ? ? ?? ? ? ? ? - ? ? note: the eeprom data memory is only available for the ht67f489.
rev. 1.60 9 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom pin assignment

rev. 1.60 10 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom pin description pin name function opt i/t o/t description pa0/i ? t ? /tck0/ ocdsda/icpda pa0 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. i ? t ? st exte ? nal inte ?? upt ? tck0 st tm0 input ocdsda st cmos ocds add ? ess/data ? fo ? ev chip only. icpda st cmos icp add ? ess/data pa1/osc ? pa3/osc1 pa6 ? pa7 pa1 ? pa3 ? pa6 ? pa7 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. osc1 osc hxt high f ? equency c ? ystal pin osc ? osc hxt high f ? equency c ? ystal pin pa ? /i ? t3/tp0_0/ ocdsck/icpck pa ? papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. i ? t3 st exte ? nal inte ?? upt 3 tp0_0 tmpc st cmos tm0 i/o ocdsck st ocds clock pin ? fo ? ev chip only. icpck st icp clock pin pa4/xt1 pa4 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. xt1 fsubc lxt low f ? equency c ? ystal pin pa5/xt ? pa5 papu pawu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high and wake-up. xt ? fsubc lxt low f ? equency c ? ystal pin pb0/a ? 0/tck3 pb0 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 0 acerl a ? a/d channel 0 tck3 st tm3 input pb1/a ? 1/tp3 pb1 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 1 acerl a ? a/d channel 1 tp3 tmpc st cmos tm3 i/o pb ? /a ?? /tp ? pb ? pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ?? acerl a ? a/d channel ? tp ? tmpc st cmos tm ? i/o pb3/a ? 3/tp1 pb3 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 3 acerl a ? a/d channel 3 tp1 tmpc st cmos tm1 i/o pb4/a ? 7/vref pb4 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 7 acerl a ? a/d channel 7 vref adcr1 a ? adc ? efe ? ence voltage input pin pb5/a ? 9 pb5 pbpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 9 acerh a ? a/d channel 9 pc0/seg8 pc0 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg8 segcr1 cmos lcd seg ? ent output pc1/seg9 pc1 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg9 segcr1 cmos lcd seg ? ent output
rev. 1.60 11 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom pin name function opt i/t o/t description pc ? /seg10 pc ? pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg10 segcr1 cmos lcd seg ? ent output pc3/seg11 pc3 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg11 segcr1 cmos lcd seg ? ent output pc4/seg1 ? pc4 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg1 ? segcr1 cmos lcd seg ? ent output pc5/seg13 pc5 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg13 segcr1 cmos lcd seg ? ent output pc6/seg14 pc6 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg14 segcr1 cmos lcd seg ? ent output pc7/seg15 pc7 pcpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg15 segcr1 cmos lcd seg ? ent output pd0/seg0 pd0 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg0 segcr0 cmos lcd seg ? ent output pd1/seg1 pd1 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg1 segcr0 cmos lcd seg ? ent output pd ? /seg ? pd ? pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg ? segcr0 cmos lcd seg ? ent output pd3/seg3 pd3 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg3 segcr0 cmos lcd seg ? ent output pd4/seg4 pd4 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg4 segcr0 cmos lcd seg ? ent output pd5/seg5 pd5 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg5 segcr0 cmos lcd seg ? ent output pd6/seg6 pd6 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg6 segcr0 cmos lcd seg ? ent output pd7/seg7 pd7 pdpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg7 segcr0 cmos lcd seg ? ent output pe0/com0 pe0 pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. com0 lcdc0 cmos lcd co ?? on output pe1/com1 pe1 pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. com1 lcdc0 cmos lcd co ?? on output pe ? /com ? pe ? pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. com ? lcdc0 cmos lcd co ?? on output pe3/com3 pe3 pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. com3 lcdc0 cmos lcd co ?? on output pe4/a ? 4/com4/ tck1 pe4 pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 4 acerl a ? a/d channel 4 com4 lcdc0 cmos lcd co ?? on output tck1 st tm1 input
rev. 1.60 1 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom pin name function opt i/t o/t description pe5/a ? 5/com5/ tck ? pe5 pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 5 acerl a ? a/d channel 5 com5 lcdc0 cmos lcd co ?? on output tck ? st tm ? input pe6/a ? 6/com6 pe6 pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 6 acerl a ? a/d channel 6 com6 lcdc0 cmos lcd co ?? on output pe7/a ? 8/com7 pe7 pepu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. a ? 8 acerh a ? a/d channel 8 com7 lcdc0 cmos lcd co ?? on output pf4/seg16/rx pf4 pfpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg16 segcr ? cmos lcd seg ? ent output rx st exte ? nal uart rx se ? ial data input pin pf5/seg17/tx pf5 pfpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg17 segcr ? cmos lcd seg ? ent output tx cmos exte ? nal uart tx se ? ial data output pin pf6/seg18/i ? t0 pf6 pfpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg18 segcr ? cmos lcd seg ? ent output i ? t0 st exte ? nal inte ?? upt 0 pf7/seg19/ i ? t1/tp0_1 pf7 pfpu st cmos gene ? al pu ? pose i/o. registe ? ena ? led pull-high. seg19 segcr ? cmos lcd seg ? ent output i ? t1 st exte ? nal inte ?? upt 1 tp0_1 tmpc st cmos tm0 i/o avdd avdd pwr adc powe ? supply vdd vdd pwr powe ? supply avss avss pwr adc g ? ound vss vss pwr g ? ound note: i/t: input type; o/t: output type opt: optional by register option pwr: power; st: schmitt t rigger input cmos: cmos output; an: analog signal lxt: low frequency crystal oscillator
rev. 1.60 13 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. ...................................................................................................................... -80ma i ol t otal .............. ....................................................................................................................... 80ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd ope ? ating voltage (hxt) f sys =4mhz ? . ? 5.5 v f sys =8mhz ? . ? 5.5 v f sys =1 ? mhz ? .7 5.5 v f sys =16mhz 4.5 5.5 v i dd ope ? ating cu ?? ent ? ? o ?? al mode ? f sys =f h ? f sub =f lxt o ? f lirc 3v ? o load ? f h =8mhz ? adc off ? wdt ena ? le 1.6 ? .4 ? a 5v 3.3 5.0 ? a ope ? ating cu ?? ent ? ? o ?? al mode ? f h =8mhz 3v ? o load ? f sys =f h / ?? adc off ? wdt ena ? le 0.9 1.5 ? a 5v ? .5 3.75 ? a 3v ? o load ? f sys =f h /4 ? adc off ? wdt ena ? le 0.7 1.0 ? a 5v ? .0 3.0 ? a 3v ? o load ? f sys =f h /8 ? adc off ? wdt ena ? le 0.6 0.9 ? a 5v 1.6 ? .4 ? a 3v ? o load ? f sys =f h /16 ? adc off ? wdt ena ? le 0.5 0.75 ? a 5v 1.5 ? . ? 5 ? a 3v ? o load ? f sys =f h /3 ?? adc off ? wdt ena ? le 0.49 0.74 ? a 5v 1.45 ? .18 ? a 3v ? o load ? f sys =f h /64 ? adc off ? wdt ena ? le 0.47 0.71 ? a 5v 1.4 ? .1 ? a ope ? ating cu ?? ent ? slow mode ? f sys = f sub (lxt ? lirc) 3v ? o load ? f sys =lxt ? adc off ? wdt ena ? le ? lxtlp=0 ? lvr ena ? le 45 75 5v 90 140 3v ? o load ? f sys =lxt ? adc off ? wdt ena ? le ? lxtlp=1 ? lvr ena ? le 40 70 5v 85 135 3v ? o load ? f sys =lirc ? adc off ? wdt ena ? le ? lvr ena ? le 40 65 5v 80 130
rev. 1.60 14 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i idle01 idle0 mode stan ? y cu ?? ent (lxt on) 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=0 ? 4 a 5v 4 8 a 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 1.5 3.0 a 5v 3.0 6.0 a i idle0 ? idle0 mode stan ? y cu ?? ent (lirc on) 3v ? o load ? adc off ? wdt ena ? le 1.5 3.0 a 5v 3.0 6.0 a i idle03 idle0 mode stan ? y cu ?? ent (lxt on) 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 ? lcd ena ? le (r t =1170k without quick cha ? ge ? v lcd =v dd ) 3 6 a 5v 6 1 ? a i idle04 idle0 mode stan ? y cu ?? ent (lxt on) 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 ? lcd ena ? le (r t =225k without quick cha ? ge ? v lcd =v dd ) 14 ? 8 a 5v ? 4 48 a i idle05 idle0 mode stan ? y cu ?? ent (lxt on) 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 ? lcd ena ? le (r t =1170k with quick charge, qct[ ? :0]=0 ? v lcd =v dd ) 5 10 a 5v 9 18 a i idle06 idle0 mode stan ? y cu ?? ent (lxt on) 3v ? o load ? adc off ? wdt ena ? le ? lxtlp=1 ? lcd ena ? le (r t =1170k with quick charge, qct[ ? :0]=7 ? v lcd =v dd ) 11 ?? a 5v 18 36 a i idle1 idle1 mode stan ? y cu ?? ent (lirc on) 3v ? o load ? adc off ? wdt ena ? le ? f sys =8mhz on 0.5 3.0 ? a 5v 1.0 6.0 ? a i sleep0 sleep0 mode stan ? y cu ?? ent (lxt o ? lirc off) 3v ? o load ? adc off ? wdt disa ? le 0. ? 1 a 5v 0.4 ? a i sleep1 sleep1 mode stan ? y cu ?? ent (lxt o ? lirc on) 3v ? o load ? adc off ? wdt ena ? le 1.5 3.0 a 5v ? .5 5.0 a v il input low voltage fo ? i/o po ? ts o ? input pins 0 0.3v dd v v ih input high voltage fo ? i/o po ? ts o ? input pins 0.7v dd v dd v gpio (except for pd0~pd7 & pe0~pe7) i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd 4 8 ? a 5v v ol =0.1v dd 10 ? 0 ? a i oh i/o po ? t sou ? ce cu ?? ent 3v v oh =0.9v dd - ? -4 ? a 5v v oh =0.9v dd -5 -10 ? a high sink i/o for led driver (pe0~pe7) i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd 8 16 ? a 5v v ol =0.1v dd ? 0 40 ? a i oh i/o po ? t sou ? ce cu ?? ent 3v v oh =0.9v dd - ? -4 ? a 5v v oh =0.9v dd -5 -10 ? a adjustable source i/o for led driver (pd0~pd7) i ol i/o po ? t sink cu ?? ent 3v v ol =0.1v dd 4 8 ? a 5v v ol =0.1v dd 10 ? 0 ? a
rev. 1.60 15 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i oh i/o po ? t sou ? ce cu ?? ent 3v v oh = 0.9v dd (iohsn[1:0]=00b ? n=0~7) - ? -4 ? a v oh = 0.9v dd (iohsn[1:0]=01b ? n=0~7) -0.67 -1.33 ? a v oh = 0.9v dd (iohsn[1:0]=10b ? n=0~7) -0.5 -1 ? a v oh = 0.9v dd (iohsn[1:0]=11b ? n=0~7) -0.33 -0.66 ? a 5v v oh = 0.9v dd (iohsn[1:0]=00b ? n=0~7) -5 -10 ? a v oh = 0.9v dd (iohsn[1:0]=01b ? n=0~7) -1.67 -3.33 ? a v oh = 0.9v dd (iohsn[1:0]=10b ? n=0~7) -1. ? 5 - ? .5 ? a v oh = 0.9v dd (iohsn[1:0]=11b ? n=0~7) -0.83 -1.67 ? a r ph pull-high resistance fo ? i/o po ? ts 3v ? 0 60 100 k 5v 10 30 50 k r t lcd total ? ias ? esiste ? 3v/5v -30 r t +30 % i tol total i/o po ? t sink cu ?? ent 5v 80 ? a i toh total i/o po ? t sou ? ce cu ?? ent 5v -80 ? a a.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu ope ? ating clock ? . ? ~5.5 dc 4 mhz ? . ? ~5.5v dc 8 mhz ? .7~5.5v dc 1 ? mhz 4.5~5.5v dc 16 mhz f sys syste ? clock (hirc) ? . ? v~5.5v 8 mhz f hirc syste ? clock (hirc) 4.5v~5.5v ta=0c to 70c - ? % 8 + ? % mhz f lirc syste ? clock (lirc) 5v ta= ? 5c -10% 3 ? +10% khz t timer tckn input pulse width 0.3 s t i ? t inte ?? upt pulse width 10 s t eerd eeprom read ti ? e 5v ? 4 t sys t eewr eeprom w ? ite ti ? e 5v ? 4 ? s t rstd syste ? reset delay ti ? e (powe ? on reset ? lvr reset ? wdtc/lvrc s/w reset) ? 5 50 100 ? s syste ? reset delay ti ? e (wdt ti ? e-out reset) 8.3 16.7 33.3 ? s t sst syste ? sta ? t-up ti ? e ? pe ? iod (wake-up f ? o ? halt) f sys =lxt/hxt 10 ? 4 t sys f sys =hirc 16 f sys =lirc ? t sreset softwa ? e reset width to reset 45 90 1 ? 0 s ote: t sys i sys
rev. 1.60 16 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom a/d converter electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d conve ? te ? ope ? ating voltage ? .7 5.5 v v adi a/d conve ? te ? input voltage 0 av dd /v ref v v ref a/d conve ? te ? refe ? ence voltage ? av dd v v bg r efe ? ence with ? u ffe ? voltage -3% 1.09 +3% v d ? l diffe ? ential ? on-linea ? ity 5v v ref =av dd =v dd t adck =0.5s -4 +4 lsb i ? l integ ? al ? on-linea ? ity 5v v ref =av dd =v dd t adck =0.5s -7 +7 lsb i adc additional powe ? consu ? ption if a/d conve ? te ? is used 3v ? o load (t adck =0.5s) 0.9 1.35 ? a 5v ? o load (t adck =0.5s) 1. ? 1.8 ? a i bg additional powe ? consu ? ption if v bg refe ? ence with buffe ? is used ? 00 300 a t adck a/d conve ? te ? clock pe ? iod 0.5 10 s t adc a/d conve ? sion ti ? e (include sa ? ple and hold ti ? e) 1 ? - ? it adc 16 t adck t ads a/d conve ? te ? sa ? pling ti ? e 4 t adck t o ?? st a/d conve ? te ? on-to-sta ? t ti ? e ? s t bgs v bg tu ? n on sta ? le ti ? e ? 00 s lvd & lvr electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr ena ? le ? ? .10v option -5% ? .10 +5% v lvr ena ? le ? ? .55v option -5% ? .55 +5% v lvr ena ? le ? 3.15v option -5% 3.15 +5% v lvr ena ? le ? 3.80v option -5% 3.80 +5% v v lvd low voltage detecto ? voltage lvde ? =1 ? v lvd = ? .0v -5% ? .0 +5% v lvde ? =1 ? v lvd = ? . ? v -5% ? . ? +5% v lvde ? =1 ? v lvd = ? .4v -5% ? .4 +5% v lvde ? =1 ? v lvd = ? .7v -5% ? .7 +5% v lvde ? =1 ? v lvd =3.0v -5% 3.0 +5% v lvde ? =1 ? v lvd =3.3v -5% 3.3 +5% v lvde ? =1 ? v lvd =3.6v -5% 3.6 +5% v lvde ? =1 ? v lvd =4.0v -5% 4.0 +5% v i lvd additional powe ? consu ? ption if lvd is used 3v lvd disable lvd enable (lvr ena ? le) 30 45 a 5v 60 90 a t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lvd low voltage width to inte ?? upt ? 0 45 90 s t lvds lvdo sta ? le ti ? e for lvr enable, lvd offon 15 s
rev. 1.60 17 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom power on reset characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd sta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr vdd v dd raising rate to ensu ? e powe ? -on reset 0.035 v/ ? s t por mini ? u ? ti ? e fo ? v dd stays at v por to ensu ? e powe ? -on reset 1 ? s
rev. 1.60 18 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution are overlapped, hence instructions are ef fectively executed in one or two cycles for most of the standard or extended instructions respectively . the exceptions to this are branch or call instructions which need one more cycle. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility . this makes the devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hirc, hxt , lxt or lirc oscillator is subdivided into four internall y generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef fectively executed in one instruction cycle. the exce ption to this are instructions where the content s of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? ? ? ? system clocking and pipelining
rev. 1.60 19 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is ex - ecuted except for instructions, such as jmp or call that demands a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register , are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register HT67F488 pc11~pc8 pcl7~pcl0 ht67f489 pc1 ? ~pc8 pcl7~pcl0 program counter the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into this register , a short program jump can be executed directly . however , as only this low byte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.60 ? 0 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is or ganized into 8 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa, ladd, laddm, ladc, ladcm, lsub, lsubm, lsbc, lsbcm, ldaa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla, land, landm, lor, lorm, lxor, lxorm, lcpl, lcpla ? rotation, rra, rr, rrca, rrc, rl a, rl , rl ca, rl c, l rr, l rra, l rrca, l rrc, lrla, lrlca, lrlc ? increment and decrement, inca, inc, deca, dec, linca, linc, ldeca, ldec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti, lsnz, lsz, lsza, lsiz, lsdz, lsiza, lsdza
rev. 1.60 ? 1 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programme d and re-programmed a lar ge number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, the flash devices of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of field programming and updating. structure the program memory has a capacity of 4k16 bits to 8k16 bits. the program memory is addressed by the program counter and also contains data, tabl e informati on and interrupt entries. table data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. device capacity HT67F488 4k16 ht67f489 8k16 special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. 0000h 0004h 002ch fffh reset interrupt vector 16 bits reset interrupt vector 16 bits 1fffh HT67F488 ht67f489 1000h program memory structure
rev. 1.60 ?? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd [m] or t abrdl [m] instructions respectively when the memory [m] is located in current page. if the memory [m] is located in other pages, the table data can be retrieved from the program memory using the ltabrd [m] or l tabrdl [m] instructions respectively. when the instruction is exec uted, the lower order table byte from the program memory will be transferred to the u ser d efned da ta me mory r egister [ m] a s sp ecifed i n t he i nstruction. t he h igher o rder t able d ata byte from the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 4k program memory of the HT67F488 device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] or l tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd [m] or ltabrd [m] instruction is executed. because the tblh register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 1.60 ? 3 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom table read program example tempreg1 db ? ; temporary register #1 in current page tempreg2 db ? ; temporary register #2 in current page : : mov a,06h ; initialise low table pointer - note that this address is ; referenced to the last page or present page mov tblp,a : : tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempreg1 ; data at program memory address f06h transferred to tempreg1 ; and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at program memory address f05h transferred to tempreg2 ; and tblh ; in this example the data 1ah is transferred to tempreg1 and ; data 0fh to register tempreg2 while the value 00h will be ; transferred the high byte register tblh : : org 0f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek writer pins mcu programming pins pin description icpda pa0 p ? og ? a ?? ing se ? ial data/add ? ess icpck pa ? p ? og ? a ?? ing clock vdd vdd powe ? supply vss vss g ? ound the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for t he c lock. t wo a dditional l ines a re re quired for t he powe r suppl y. t he t echnical de tails regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature.
rev. 1.60 ? 4 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom during the programming process, taking control of the p a0 and p a2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
note: * may be resistor or capacitor . the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. on-chip debug support C ocds there is an ev chip named ht67v489 which is used to emulate the HT67F488/ht67f489 series of devices. the ht67v489 device also provides the on-chip debug function to debug the HT67F488/ht67f489 s eries of devices during development proces s. the devices , h t67f488/ ht67f489 and ht67v489, are almost functional compatible except the on-chip debug function and package types. users can use the ht67v489 device to emulate the HT67F488/ht67f489 series of de vices be haviors by c onnecting t he ocdsda a nd ocdsck pi ns t o t he holt ek ht - ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ht67v489 ev chip for debugging, the corresponding pin functions shared with the ocdsda and ocdsck pins in the HT67F488/ ht67f489 series of devices will have no ef fect in the ht67v489 ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip de ? ug suppo ? t data/add ? ess input/output ocdsck ocdsck on-chip de ? ug suppo ? t clock input vdd vdd powe ? supply vss vss g ? ound
rev. 1.60 ? 5 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom ram data memory the dat a mem ory is an 8-bit wide ram inte rnal me mory and is the locat ion where te mporary information is stored. divided into two types, the frst of data memory is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. m any of these registers can be read from and w ritten to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the data memory is divided into several sectors, all of which are implemented in 8-bit wide memory. each of the data memory sectors is categorized into two types, the special purpose data memory and the general purpose data memory. the start address of the special purpose data memory for all devices is the address 00h while the start address of the general purpose data memory is the address 80h. the special purpose data memory registe rs are ac cessible in al l se ctors, wi th the exc eption of the ee c registe r at address 40h, which is only accessible in sector 1. device capacity sectors HT67F488 ht67f489 gene ? al pu ? pose: ? 56 8 0: 80h~ffh 1: 80h~93h (fo ? lcd) ? : 80h~ffh 00h 7fh 80h ffh special pu?pose data me?o?y gene?al pu?pose data me?o?y secto? 0 secto? 1 secto? 1 lcd data me?o?y secto? ? 93h 40h: eec (only availa?le in secto? 1 fo? ht67f489) data memory structure
rev. 1.60 ? 6 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom data memory addressing for the devices that support the extended instructions, there is no bank pointer for data memory addressing. for data memory the desired sector is pointed by the mp1h or mp2h register and the certain data memory address in the selected sector is specifed by the mp1l or mp2l register when using indirect addressing access. direct addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. for the accessed data memory which is located in any data memory sectors e xcept se ctor 0, t he e xtended i nstructions c an be use d t o a ccess t he da ta m emory i nstead of u sing t he i ndirect a ddressing a ccess. t he m ain d ifference b etween st andard i nstructions a nd extended instructions is that the data memory address m in the extended instructions has 10 valid bits, the high byte indicates a sector and the low byte indicates a specifc address. general purpose data memory there are 256 bytes of general purpose memory which are arranged in 80h~ffh of sector 0, sector 2 separately . and another 20 bytes of lcd memory are mapped in 80h~93h of sector 1. all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later . it is this area of ram memory that is known as general purpose data memory. the general purpose data memory is fully accessible by the user program for both read and writing operations. by using the "set [m].i" and "clr [m].i" instructi ons individual bits can be set or reset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, a re st ored. t hey a re ov erlapped i n a ny se ctor. most of t he re gisters a re bo th readable and writable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locations that are unused before 80h, any read instruction to these addresses will return the value "00h".
rev. 1.60 ? 7 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom 00h iar0 01h mp0 0?h iar1 03h mp1l 04h 05h acc 06h pcl 07h tblp 08h tblh 09h tbhp 0ah status 0bh tm1al 0ch eea 0dh tm1dh 0eh eed 0fh pe 10h tm0dl 11h tm0dh 1?h 19h wdtc 18h tbc 1bh 1ah 1dh 1ch 1fh lvdc 1eh 13h 14h tm0rpl 15h tm0rph 16h 17h tm1c0 sector 0, 1 fsubc i?teg i?tc0 i?tc? mfi0 mfi1 mfi3 pawu papu pa pbpu pb pbc acerh tm0c0 tm0c1 ?0h ?1h ??h ?9h ?8h ?bh ?ah ?dh ?ch ?fh ?eh ?3h ?4h ?5h ?6h ?7h 30h 31h 3?h 39h 38h 3bh 3ah 3dh 3ch 3fh 3eh 33h 34h 35h 36h 37h 40h eec 41h usr 4?h ucr1 43h tm3dh 47h tm3al 48h tm?dl 49h tm3ah 4ah 4bh 4ch 4dh tm3c1 4eh tm3dl 4fh 50h 51h 5?h 58h 53h 54h 55h 56h 57h sector 0 sector 1 tm?c0 tm?c1 tm?dh tm?al tm?ah tm3c0 60h 61h mp1h iar? mp?l mp?h tm0al tm0ah tm1c1 tm1dl tm1ah 44h 45h 46h 59h 5ah 5bh 5ch 5dh 5eh 5fh lcdc0 lcdc1 segcr0 segcr1 segcr? pcpu pc pcc pdpu pd pdc 6?h 63h 64h 65h 66h 67h 68h 69h pepu pec pfpu pf pfc 6ah 6bh 6dh 6ch 6eh 6fh tmpc 70h 71h 7?h 73h 74h 75h 76h 77h 78h 79h 7ah 7bh 7dh 7ch 7eh 7fh : unused? ?ead as 00h smod ctrl i?tc1 mfi? pac acerl ucr? brg txr/rxr lvrc iohr0 iohr1 mfi4 adcr1 adrl adrh adcr0 special purpose data memory
rev. 1.60 ? 8 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom special function register description most of the special function register details will be described in the relevant functional sections, however several registers require a separate description in this section. indirect addressing register C iar0, iar1, iar2 the indirect addressing registers, iar0, iar1 and iar2, although having their locations in normal ram r egister sp ace, d o n ot a ctually p hysically e xist a s n ormal r egisters. t he m ethod o f i ndirect addressing for ram da ta m anipulation use s t hese indi rect addre ssing re gisters a nd me mory pointers, i n c ontrast t o di rect m emory a ddressing, where t he a ctual m emory a ddress i s spe cifed. actions on t he iar0, iar1 a nd iar2 re gisters wi ll re sult i n no a ctual re ad or writ e ope ration t o these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair , iar0 and mp0 can together access data only from sector 0 while the iar1 register together with mp1l/mp1h register pair and iar2 register together with mp2l/mp2h register pair can access data from any data memory sector . as the indirec t addressing re gisters are not physi cally i mplemented, rea ding t he indirec t addressing registers indirectl y will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1l, mp1h, mp2l, mp2h five memory pointers, known as mp0, mp1l, mp1h, mp2l and mp2h, are provided. these memory pointers are phys ically implemented in the d ata m emory and can be manipulated in the same wa y a s n ormal r egisters p roviding a c onvenient wa y wi th wh ich t o a ddress a nd t rack d ata. when any operati on to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from sector 0, while mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all data sectors according to the corresponding mp1h or mp2h register. direct addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. the following example shows how to clear a sector of four data memory locations already defned as locations adres1 to adres4.
rev. 1.60 ? 9 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom indirect addressing program example 1 data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section a t 0 code org 00h start: mov a, 04h ; setup size of block mov b lock, a mov a, o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov mp0, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr iar0 ; c lear t he d ata a t ad dress d efned b y m p0 inc m p0 ; increment memory pointer sdz b lock ; check if last memory location has been cleared jmp loop continue: indirect addressing program example 2 data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: mov a, 04h ; setup size of block mov block, a mov a, 01h ; setup the memory sector mov mp1h, a mov a , o ffset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p1l, a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar1 ; c lear t he d ata a t a ddress d efned b y m p1l inc m p1l ; i ncrement m emory po inter m p1l sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.60 30 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom direct addressing program example using extended instructions data .section data temp db ? code .section at 0 code org 00h start: lmov a, [m] ; move [m] data to acc lsub a, [m+1] ; compare [m] and [m+1] data snz c ; [m]>[m+1]? jmp continue ; no lmov a, [m] ; yes, exchange [m] and [m+1] data mov temp, a lmov a, [m+1] lmov [m], a mov a, temp lmov [m+1], a continue: note: here m is a data memory address located in any data memory sectors. for example, m=1f0h, it indicates address 0f0h in sector 1. accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, whe n t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted.
rev. 1.60 31 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the sc fag, cz fag, zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/ logical o peration a nd sy stem m anagement fa gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac, c, sc and cz fags generally refect the status of the latest operations. ? sc is the result of the xor operation which is performed by the ov fag and the msb of the current instruction operation result. ? cz is the operational result of dif ferent fags for dif ferent instuctions. refer to register defnitions for more details. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also af fected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power -up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cle ared by a system power -up or executing the clr wdt or hal t instruction. to is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.60 3 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom status register bit 7 6 5 4 3 2 1 0 ? a ? e sc cz to pdf ov z ac c r/w r/w r/w r r r/w r/w r/w r/w por x x 0 0 x x x x x unknown bit 7 sc : the result of the xor operation which is performed by the ov fag and the msb of the instruction operation result. bit 6 cz : the the operational result of different fags for different instructions. for sub/subm/lsub/lsubm instructions, the cz fag is equal to the z fag. for sbc/sbcm/lsbc/lsbcm instructions, the cz flag is the and operation result which is performed by the previous operation cz fag and current operation zero fag. for other instructions, the cz fag will not be affected. bit 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.60 33 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom eeprom data memory the ht 67f489 de vice c ontains a n a rea of i nternal e eprom da ta me mory. e eprom, whi ch stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a whole new host of appli cation possibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 648 bits for the device. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory . read and write operations to the eeprom are carried out in single byte operations using an address and data register in sector 0 and a single control register in sector 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in sector 0, they can be directly accessed in the same was as any other special function register . the eec register however , being located in sector1, cannot be di rectly a ddressed di rectly a nd c an onl y be re ad from or wri tten t o i ndirectly usi ng t he mp1l / mp1h memory pointer and indirec t addressing register , iar1. becau se the eec control register is located at address 40h in sector 1, the mp1l memory pointer low byte must frst be set to the value 40h and the mp1h memory pointer high byte set to the value 01h before any operations on the eec register are executed. eeprom register list name bit 7 6 5 4 3 2 1 0 eea d5 d4 d3 d ? d1 d0 eed d7 d6 d5 d4 d3 d ? d1 d0 eec wre ? wr rde ? rd eea register bit 7 6 5 4 3 2 1 0 ? a ? e d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 d5~d0 : data eeprom address data eeprom address bit 5 ~ bit 0
rev. 1.60 34 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom eed register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 ? a ? e wre ? wr rde ? rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.60 35 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to initiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should als o frs t be cleared before implementing any write operations, and then set again after the write cycle has started. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on mp1l/mp1h and mp2l/mp2h will be reset to zero, which means that data memory sector 0 will be selected. as the eeprom control register is located in sector 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 1.60 36 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by e nsuring t hat t he w rite e nable bi t i s norm ally c leared t o z ero whe n not wri ting. also the memory pointer high byte, mp1h or mp2h, could be normally cleared to zero as this would inhibit access to sector 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after t he wri te c ycle sta rts. not e t hat t he de vice should not e nter t he idl e or sle ep m ode unt il the e eprom r ead o r wr ite o peration i s t otally c omplete. ot herwise, t he e eprom r ead o r wr ite operation will fail. programming examples reading data from the eeprom - polling method mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, 0 40h ; se tup m emory p ointer m p1l mov mp1l, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; se tup m emory p ointer m p1h mov mp1h, a set iar1.1 ; s et r den b it, e nable r ead o perations set iar1.0 ; s tart r ead c ycle - s et r d b it back: sz iar1.0 ; c heck f or re ad c ycle e nd jmp back clr iar1 ; d isable ee prom re ad/write clr mp1h mov a, ee d ; m ove re ad d ata t o re gister mov read_data, a writing data to the eeprom - polling method mov a, ee prom_adres ; u ser d efned ad dress mov eea, a mov a, e eprom_data ; u ser d efned da ta mov eed, a mov a, 0 40h ; se tup m emory p ointer m p1l mov mp1l, a ; mp1 p oints t o e ec r egister mov a, 0 1h ; se tup m emory p ointer m p1h mov mp1h, a clr emi set iar1.3 ; s et w ren b it, e nable w rite o perations set iar1.2 ; s tart w rite c ycle - s et w r b it C e xecuted i mmediately a fter set wren b it set emi back: sz iar1.2 ; c heck f or wr ite c ycle e nd jmp back clr iar1 ; d isable ee prom re ad/write clr mp1h
rev. 1.60 37 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom oscillators various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide ra nge of bot h fa st and slow system oscill ators. the higher freque ncy oscillators provide higher performance but carry with it the disadvantage of higher power requirements, wh ile t he o pposite i s o f c ourse t rue f or t he l ower f requency o scillators. w ith t he capability of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins inte ? nal high speed rc hirc 8mhz exte ? nal high speed c ? ystal hxt 400khz~16mhz osc1/osc ? inte ? nal low speed rc lirc 3 ? khz exte ? nal low speed c ? ystal lxt 3 ? .768khz xt1/xt ? oscillator types system clock confgurations there are four methods of generating the system clock, two high speed oscillators and two low speed oscillators. the high speed oscillator are the internal 8mhz rc oscill ator - hirc and the external crystal/ceramic oscillator - hxt . the two low speed oscillators are the internal 32khz rc oscillator - lirc and the external 32.768khz crystal oscillator - lxt. selecting whether the low or high speed oscillator is us ed as the s ystem os cillator is implemented us ing the h lclk bit and ck s2~cks0 bits i n t he smod r egister a nd a s t he syst em c lock c an b e d ynamically se lected. no te t hat t wo oscillator selection s must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator.
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rev. 1.60 38 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom external crystal/ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or re sonator m anufacturer's spe cifcation. an a dditional c onfguration op tion m ust be se tup to confgure the device according to whether the oscillator frequency is high, defned as equal to or above 1mhz, or low, which is defned as below 1mhz. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the mcu as possible.
? ? ?? crystal/resonator oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0pf 0pf 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf 455khz (see ? ote ? ) 100pf 100pf ? ote: 1. c1 and c ? values a ? e fo ? guidance only. 2. xtal mode confguration option: 455khz. crystal recommended capacitor values internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as a f ixed f requency o f 8 mhz. de vice t rimming d uring t he manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins are free for use as normal i/o pins.
rev. 1.60 39 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via the fsubc register . this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compen sation due to dif ferent crystal manufacturing toleranc es. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microco ntroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specification. the external parallel feedback resistor, r p , is required. the fsubc register determine s if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure thatthe c rystal a nd a ny a ssociated re sistors a nd c apacitors a long wi th i nterconnectinglines a re a ll located as close to the mcu as possible.
? ? ? ?? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3 ? .768khz 10pf 10pf ? ote: 1. c1 and c ? values a ? e fo ? guidance only. ? . r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values
rev. 1.60 40 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the fsubc register. fsubc register bit 7 6 5 4 3 2 1 0 ? a ? e lxtlp fsub6 fsub5 fsub4 fsub3 fsub ? fsub1 fsub0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 1 0 1 0 bit 7 lxtlp : lxt low power control 0: quick start mode 1: low power mode bit 6~0 fsub6~fsub0 : f sub clock source selection 0101010: lirc 1010101: lxt others: mcu reset after power on, the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into t he l ow-power m ode b y se tting t he l xtlp b it h igh. t he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it shou ld be no ted t hat, no m atter wha t c ondition t he l xtlp bi t i s se t t o, t he l xt osc illator wi ll always function normally , the only dif ference is that it will take more time to start up if in the low- power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via the fsubc register . it is a fully integrated rc oscillator with a typical frequency of 32khz a t 5 v, r equiring n o e xternal c omponents f or i ts i mplementation. de vice t rimming d uring the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%.
rev. 1.60 41 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the m ain sy stem c lock, c an c ome f rom e ither a h igh f requency f h o r l ow f requency f sub so urce, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system c lock c an be sour ced fr om the hirc /hxt osc illator. t he l ow spe ed syst em c lock sour ce can be sourced from internal clock f sub . if f sub is selected then it can be sourced by either the lxt or lirc oscill ator, sele cted by the fsub6~fsub0 bits in the fsubc regi ster . the othe r choi ce, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64.
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? ? ?? ? ? system clock confguration note: w hen t he syst em c lock sou rce f sys i s swi tched t o f sub f rom f h , t he h igh spe ed o scillation wi ll st op t o conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.60 4 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power. operating mode description cpu f sys f sub f tbc ? ormal mode on f h ~f h /64 on on slow mode on f sub on on idle0 mode off off on on idle1 mode off on on on sleep0 mode off off off off sleep1 mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator hirc/hxt . the high speed oscillator will however frst be divided by a rati o ranging from 1 to 64, the ac tual rati o bei ng sel ected by the cks2~cks0 and hlcl k bits in the smod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f sub clock will be stopped too, and the w atchdog t imer function is disabled. in this mode, the lvden is must set to 0. if the lvden is set to 1, it wont enter the sleep0 mode. sleep1 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f sub clock will continue to operate if the lvden is 1 or the w atchdog t imer function is enabled. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl regi ster i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu, the system oscillator will be stopped , the low frequency clock f sub will be on.
rev. 1.60 43 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator . in the idle1 mode the low frequency clock f s ub will be on. note: if l vden=1 and the s leep or id le mode is entered, the l vd and bandgap functions will not be dis abled, and the f sub clock w ill be forced to be enabled . in s leep mode, other peripheral will disable except wdt , lvd if enable in sleep 1. control register a single register, smod, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 ? a ? e cks ? cks1 cks0 lto hto idle ? hlclk r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 1 1 bit 7~5 : the system clock selection when hlclk is 0 000: f sub (f lxt or f lirc ) 001: f sub (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0 bit 3 : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake- up has occurred, the fag will change to a high level after 15~16 clock cycles if the hirc/hxt oscillator is used.
rev. 1.60 44 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f sub clock will be selected. when system clock sw itches from the f h clock to the f sub clock and the f h clock will be automatically switched of f to conserve power. ? a ? e fsyso ? fsubf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 x unknown bit 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~4 unimplemented, read as 0 bit 3 fsubf : fsubc control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the fsub6~fsub0 bits in the fsubc register contains any undefned values. this bit can only be cleared to 0 by the application program. bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program.
rev. 1.60 45 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condit ion of the idl en bit in the smod regi ster and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal cloc k sources will also stop running, which may af fect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when the device moves between the various operating modes.

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rev. 1.60 46 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the sl ow mode is sourc ed from the lxt or the lirc osci llators and the refore requi res these oscillators to be stable before full mode switching occurs. this is monitored using the l to bit in the smod register.
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rev. 1.60 47 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be se t t o 1 or hl clk bi t i s 0, but cks2~cks0 i s se t t o 010, 011, 100, 101, 110 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the ht o bit is checke d. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
? ? ? ? ? ? ?? ?? ? -?? ? ? ? ? ?? ?? ? -?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? -?? ?
rev. 1.60 48 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom entering the sleep0 mode there is only one way for the devic e to enter the sleep0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the sleep1 mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt or l vd on. w hen t his i nstruction i s e xecuted unde r t he c onditions de scribed a bove, t he following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruction, but the t ime base clock f tbc and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, t ime base clock f tbc and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition.
rev. 1.60 49 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power-up or executing the clear w atchdog t imer instructions and is set when executing the hal t instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled.
rev. 1.60 50 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f sub , t he f sub clock is sourced from lirc or lxt oscillator select ed by the fsubc register . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the act ual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v . however , it should be noted that this specifed internal clock period can vary with v dd , temperat ure and process variations . the lxt oscillator is supplied by an external 32.768khz crystal. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. wdtc register bit 7 6 5 4 3 2 1 0 ? a ? e we4 we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control 10101: disable 01010: enable others: reset mcu when these bits are changed by the environmental noise to reset the microcontroller , the reset operation will be activated after a delay time, t sreset and the wrf bit in the ctrl register will be set to 1. bit 2~0 : wdt time-out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub
rev. 1.60 51 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom ctrl register bit 7 6 5 4 3 2 1 0 ? a ? e fsyso ? fsubf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 x unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~4 unimplemented, read as 0 bit 3 fsubf : fsubc control register software reset fag described elsewhere. bit 2 lvrf : lvr function reset fag described elsewhere. bit 1 lrf : lvr control register software reset fag described elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the w atchdog t imer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. w ith regard to t he w atchdog t imer e nable/disable f unction, t here a re a lso fv e b its, w e4~we0, i n t he w dtc register to of fer additional enable/disable and reset control of the w atchdog t imer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bits value is equal to 01010b. if the we4~we0 bits are set to any other values by the environmental noise or software setting, except 01010b and 10101b, it will reset the device after a delay time, t sreset . after power on these bits will have the value of 01010b. we4 ~ we0 bits wdt function 10101b disa ? le 01010b ena ? le any othe ? value reset mcu watchdog timer enable/disable control under normal program operation, a w atchdog t imer time-out will initialise a device reset and set the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit f led, the s econd is us ing the w atchdog t imer s oftware clear instructions and the third is via a halt instruction.
rev. 1.60 5 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 8ms for the 2 8 division ration. clr wdt instruction 8-stage divider wdt prescaler we4~we0 bits wdtc register reset mcu lxt f sub f sub /2 8 8-to-1 mux clr ws2~ws0 (f sub /2 8 ~ f sub /2 18 ) wdt time-out (2 8 /f sub ~ 2 18 /f sub ) lirc m u x fsubc fsub6~fsub0 bits watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the w atchdog t imer overfows and resets. all types of reset operations result in dif ferent register condition s being setup. another reset exists in the form of a low v oltage reset, l vr, where a full res et is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a reset can occur, through events occurring internally. power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all i/o ports will be frst set to inputs. v dd powe?-on reset sst ti?e-out t rstd note: t rstd is power-on delay, typical time=50ms power-on reset timing chart
rev. 1.60 53 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom low voltage reset lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set to 1. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the l vd & l vr electrical characteristics. if the low supply voltage state does not exceed this value, the l vr will ignore the low supply voltag e and will not perform a reset function. the actual v lvr value can be selected by the l vs bits in the l vrc register . if the l vs7~lvs0 bits are changed to some certain values by the environmental noise or software setting, the l vr will reset the device after a delay time, t sreset . when t his ha ppens, t he l rf bi t i n t he ct rl re gister wil l be set t o 1. afte r power on t he re gister will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode. note: t rstd is power-on delay, typical time=50ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 ? a ? e lvs7 lvs6 lvs5 lvs4 lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr voltage select 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value: generates mcu reset -- lvrc register is reset to por value when an actual low voltage condit ion occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be a ctivated a fter t he l ow vol tage c ondition ke eps m ore t han a t lvr t ime. in t his situation the register contents will remain the same after such a reset occurs. any register value, other than the four defned l vr values above, will also result in the generation of an m cu res et. the res et operation w ill be activated after a delay time, t sreset . however in this situation the register contents will be reset to the por value.
rev. 1.60 54 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom ? ctrl register bit 7 6 5 4 3 2 1 0 ? a ? e fsyso ? fsubf lvrf lrf wrf r/w r/w r/w r/w r/w r/w por 0 0 x 0 0 x unknown bit 7 fsyson : f control in idle mode described elsewhere. bit 6~4 unimplemented, read as 0 bit 3 fsubf : fsubc control register software reset fag described elsewhere. bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit can be clear to 0, but can not set to 1. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag described elsewhere. watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as l vr reset except that the watchdog time-out fag t o will be set to "1". note: t rstd is power-on delay, typical time= 16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc/hxt. the t sst is 1024 clock for lxt. the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart
rev. 1.60 55 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing ? o ?? al o ? slow mode ope ? ation 1 u wdt ti ? e-out ? eset du ? ing ? o ?? al o ? slow mode ope ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? sleep mode ope ? ation ? ote: u stands fo ? unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? a ? counte ? reset to ze ? o inte ?? upts all inte ?? upts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins counting ti ? e ? /event counte ? ti ? e ? counte ? will ? e tu ? ned off input/output po ? ts i/o po ? ts will ? e setup as inputs and a ? 0~a ? 9 as a/d input pins stack pointe ? stack pointe ? will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes h ow e ach t ype o f re set a ffects e ach of t he m icrocontroller i nternal re gisters. not e t hat where m ore t han one pa ckage t ype e xists t he t able wi ll re fect t he sit uation for t he l arger pa ckage type. register power on reset lvr reset wdt time-out (normal operation) wdt time-out (halt) iar0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu iar1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp1h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu iar ? xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp ? l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu mp ? h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---x xxxx ---u uuuu ---u uuuu ---u uuuu status xx00 xxxx uuuu uuuu uu1u uuuu uu11 uuuu smod 000- 0011 000- 0011 000- 0011 uuu- uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu ctrl 0--- 0x00 0--- uuuu 0--- uuuu 0--- uuuu i ? teg 0000 0000 0000 0000 0000 0000 uuuu uuuu
rev. 1.60 56 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom register power on reset lvr reset wdt time-out (normal operation) wdt time-out (halt) wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 0011 -111 uuuu -uuu i ? tc0 -000 0000 -000 0000 -000 0000 -uuu uuuu i ? tc1 0000 0000 0000 0000 0000 0000 uuuu uuuu i ? tc ? -000 -000 -000 -000 -000 -000 -uuu -uuu mfi0 --00 --00 --00 --00 --00 --00 --uu --uu mfi1 --00 --00 --00 --00 --00 --00 --uu --uu mfi ? --00 --00 --00 --00 --00 --00 --uu --uu mfi3 --00 --00 --00 --00 --00 --00 --uu --uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu --00 0000 --00 0000 --00 0000 --uu uuuu pb --11 1111 --11 1111 --11 1111 --uu uuuu pbc --11 1111 --11 1111 --11 1111 --uu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 0000 ---- 0000 ---- 0000 ---- uuuu ---- pf 1111 ---- 1111 ---- 1111 ---- uuuu ---- pfc 1111 ---- 1111 ---- 1111 ---- uuuu ---- tmpc ---0 0000 ---0 0000 ---0 0000 ---u uuuu iohr0 0000 0000 0000 0000 0000 0000 uuuu uuuu iohr1 0000 0000 0000 0000 0000 0000 uuuu uuuu adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 0000 0110 0000 0110 0000 uuuu uuuu adcr1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu acerl 1111 1111 1111 1111 1111 1111 uuuu uuuu acerh ---- --11 ---- --11 ---- --11 ---- --uu
rev. 1.60 57 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom register power on reset lvr reset wdt time-out (normal operation) wdt time-out (halt) tm0c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm0rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0rph ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm ? c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? dh ---- --00 ---- --00 ---- --00 ---- --uu tm ? al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm ? ah ---- --00 ---- --00 ---- --00 ---- --uu tm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh ---- --00 ---- --00 ---- --00 ---- --uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah ---- --00 ---- --00 ---- --00 ---- --uu fsubc 0010 1010 0010 1010 0010 1010 uuuu uuuu lcdc0 0000 -000 0000 -000 0000 -000 uuuu -uuu lcdc1 000- 0000 000- 0000 000- 0000 uuu- uuuu segcr0 0000 0000 0000 0000 0000 0000 uuuu uuuu segcr1 0000 0000 0000 0000 0000 0000 uuuu uuuu segcr ? ---- 0000 ---- 0000 ---- 0000 ---- uuuu eea --00 0000 --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu usr 0000 1011 0000 1011 0000 1011 uuuu uuuu ucr1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu ucr ? 0000 0000 0000 0000 0000 0000 uuuu uuuu brg xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu txr/rxr xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu note: u stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.60 58 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the devic e provides bidirectional input/output lines labeled with port names p a~pf. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu6 pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 papu papu7 papu6 papu5 papu4 papu3 papu ? papu1 papu0 pa pa7 pa6 pa5 pa4 pa3 pa ? pa1 pa0 pac pac7 pac6 pac5 pac4 pac3 pac ? pac1 pac0 pbpu pbpu5 pbpu4 pbpu3 pbpu ? pbpu1 pbpu0 pb pb5 pb4 pb3 pb ? pb1 pb0 pbc pbc5 pbc4 pbc3 pbc ? pbc1 pbc0 pcpu pcpu7 pcpu6 pcpu5 pcpu4 pcpu3 pcpu ? pcpu1 pcpu0 pc pc7 pc6 pc5 pc4 pc3 pc ? pc1 pc0 pcc pcc7 pcc6 pcc5 pcc4 pcc3 pcc ? pcc1 pcc0 pdpu pdpu7 pdpu6 pdpu5 pdpu4 pdpu3 pdpu ? pdpu1 pdpu0 pd pd7 pd6 pd5 pd4 pd3 pd ? pd1 pd0 pdc pdc7 pdc6 pdc5 pdc4 pdc3 pdc ? pdc1 pdc0 pepu pepu7 pepu6 pepu5 pepu4 pepu3 pepu ? pepu1 pepu0 pe pe7 pe6 pe5 pe4 pe3 pe ? pe1 pe0 pec pec7 pec6 pec5 pec4 pec3 pec ? pec1 pec0 pfpu pfpu7 pfpu6 pfpu5 pfpu4 pf pf7 pf6 pf5 pf4 pfc pfc7 pfc6 pfc5 pfc4 : unimplemented, read as 0 pawun: pa wake-up function control 0: disable 1: enable pan/pbn/pcn/pdn/pen/pfn: i/o data bit 0: data 0 1: data 1 pacn/pbcn/pccn/pdcn/pecn/pfcn: i/o type selection 0: output 1: input papun/pbpun/pcpun/pdpun/pepun/pfpun: pull-high function control 0: disable 1: enable
rev. 1.60 59 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high r esistors a re se lected u sing r egisters p apu~pfpu, a nd a re i mplemented u sing we ak pmos transistors. port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 ? a ? e pawu7 pawu6 pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu7~pawu0 : port a bit 7 ~ bit 0 w ake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac~pfc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for these pins, the chosen function of the multi-functio n i/o pins is selected by a series of registers via the application program control.
rev. 1.60 60 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.
?? ? ? ? ? ?? ? ? ? - ? generic input/output structure

? ?
? ? ? ? - ? ? - ? ? ? ? a/d input/output structure
rev. 1.60 61 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pfc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port da ta re gisters, p a~pf, a re fi rst progra mmed. se lecting whi ch pi ns a re i nputs a nd whi ch a re outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming i ndividual b its i n t he p ort c ontrol re gister u sing t he set [m ].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.60 6 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions each device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact and periodic tm sections. introduction these devices contain four tms having a reference name of tm0, tm1, tm2 and tm3. each individual tm can be categorised as a certain type, namely compact t ype tm or periodic t ype tm. although si milar i n n ature, t he d ifferent t m t ypes v ary i n t heir f eature c omplexity. t he c ommon features to all of the compact and periodic tms will be described in this section, the detailed operation regardin g each of the tm types will be described in separate sections. the main features and differences between the two types of tms are summarised in the accompanying table. function ctm ptm ti ? e ? /counte ? i/p captu ? e co ? pa ? e match output pwm channels 1 1 single pulse output 1 pwm align ? ent edge edge pwm adjust ? ent pe ? iod & duty duty o ? pe ? iod duty o ? pe ? iod tm function summary this chip contains a specifc number of either compact t ype and periodic t ype tm units which are shown in the table together with their individual reference names, tm0~tm3. tm0 tm1 tm2 tm3 10- ? it ptm 10- ? it ctm 10- ? it ctm 10- ? it ctm tm name/type reference tm operation the t wo di fferent t ypes of t m of fer a di verse ra nge of func tions, from sim ple t iming ope rations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.60 63 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact t ype and periodic t ype tms each have two internal interrupts, one for each of the internal c omparator a or c omparator p , whi ch ge nerate a t m i nterrupt whe n a c ompare m atch condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tm s each have one or tw o output pins w ith the label tp n. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situat ion occurs. the external tpn output pin is also the pin where the tm g enerates t he pw m o utput wa veform. as t he t m o utput p ins a re p in-shared wi th o ther f unction, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. t he num ber of out put pi ns for e ach t m t ype i s di fferent, t he de tails a re provi ded i n t he accompanying table. periodic t ype tm output pin names have a _n suf fix. pin names that include a _0 or _1 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. tm0 tm1 tm2 tm3 tp0_0 ? tp0_1 tp1 tp ? tp3 tm output pins tm input/output pin control registers selecting to have a tm input/outpu t or whether to retain its other shared functions is implemented using one register with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output if reset to zero the pin will retain its original other functions.
rev. 1.60 64 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom

tm0 function pin control block diagram

tm1 function pin control block diagram

tm2 function pin control block diagram tm3 function pin control block diagram
rev. 1.60 65 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tmpc register bit 7 6 5 4 3 2 1 0 ? a ? e t3cp t ? cp t1cp t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as 0 bit 4 t3cp : tp3 pin control 0: disable 1: enable bit 3 t2cp : tp2 pin control 0: disable 1: enable bit 2 t1cp : tp1 pin control 0: disable 1: enable bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable programming considerations the tm counter registers and the capture/compare ccra and ccrp registers, being 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buffer and its rela ted low byte only takes place when a write or read operation to its corresponding high byte is execu ted. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing the register is carried out in a specific way described above, it is recommended to use the mov instruction to access the ccra and ccrp low byte registers, named tmxal and tmxrpl, using the following access procedures. accessing the ccra or ccrp l ow by te re gister wi thout fo llowing t hese a ccess pro cedures wi ll re sult i n un predictable values. data bus 8-?it buffe? tmxdh tmxdl tmxah tmxal tm counte? registe? (read only) tm ccra registe? (read/w?ite) tmxrph tmxrpl tm ccrp registe? (read/w?ite)
rev. 1.60 66 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. w rite data to low byte tmxal or tmxrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah or tmxrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte tmxdh, tmxah or tmxrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxrpl C this step reads data from the 8-bit buffer. periodic type tm C ptm the pe riodic t ype t m c ontains fv e o perating m odes, wh ich a re c ompare ma tch ou tput, t imer/ event counter , capture input, single pulse output and pwm output modes. the periodic tm can be controlled with an external input pin and can drive two external output pin. name tm no. tm input pin tm output pin 10- ? it ptm 0 tck0 tp0_0 ? tp0_1 periodic tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with the ccra and ccrp registers. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.60 67 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom
? ? ? ? ? ?
? ?? - ?
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? ? ? ??? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? periodic type tm block diagram (n=0) periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrp value. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 tmnc0 tnpau tnck ? tnck1 tnck0 tno ? tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr tmndl d7 d6 d5 d4 d3 d ? d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d3 d ? d1 d0 tmnah d9 d8 tmnrpl d7 d6 d5 d4 d3 d ? d1 d0 tmnrph d9 d8 10-bit periodic tm register list (n=0)
rev. 1.60 68 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tmnc0 register bit 7 6 5 4 3 2 1 0 ? a ? e tnpau tnck ? tnck1 tnck0 tno ? r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f h 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tm output control bit, when the bit changes from low to high. bit 2~0 unimplemented, read as 0
rev. 1.60 69 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tmnc1 register bit 7 6 5 4 3 2 1 0 ? a ? e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tncapts tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operation mode 00: compare match output mode 01: capture input mode 10: pwm output mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpn_0, tpn_1, tckn 01: input capture at falling edge of tpn_0, tpn_1, tckn 10: input capture at falling/rising edge of tpn_0, tpn_1, tckn 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when these bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit. note that the output level requeste d by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the tnio1 and tnio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running.
rev. 1.60 70 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm output mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm output mode/single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0, tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 tncapts : tmn capture trigger source select 0: from tpn_0, tpn_1 pin 1: from tckn pin bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm, single pulse or input capture mode. tmndl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d5 d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8
rev. 1.60 71 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tmnal register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmnah : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 tmnrpl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnrpl : tmn ccrp low byte register bit 7 ~ bit 0 tmn 10-bit ccrp bit 7 ~ bit 0 tmnrph register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmnrph : tmn ccrp high byte register bit 1 ~ bit 0 tmn 10-bit ccrp bit 9 ~ bit 8
rev. 1.60 7 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom periodic type tm operating modes the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to se lect t his m ode, b its t nm1 a nd t nm0 i n t he t mnc1 r egister, sh ould b e a ll c leared t o 0 0 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare match from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow . here both the tnaf and tnpf interrupt request fags for comparator aand comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr i s h igh n o t npf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match from comparator p , will have no ef fect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1, tnio0 bits are zero then no pin change will take place.
rev. 1.60 73 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3 ff ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ti?e ccrp =0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0 ; tnm [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag ?ote tnio [1:0 ] = 10 active high output select he?e tnio [1:0 ] = 11 toggle output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol is high compare match output mode C tncclr = 0 (n=0) note: 1. w ith tncclr = 0 C a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to initial state by a tnon bit rising edge
rev. 1.60 74 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3 ff ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ti?e ccra =0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1 ; tnm [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag ?ote tnio [1:0 ] = 10 active high output select he?e tnio [1:0 ] = 11 toggle output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol is high tnpf not gene?ated ?o tnaf flag gene?ated on ccra ove?flow output does not change compare match output mode C tncclr = 1 (n=0) note: 1. w ith tncclr = 1 C a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to initial state by a tnon rising edge 4. the tnpf fag is not generated when tncclr = 1
rev. 1.60 75 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should all be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to se lect t his mode , bit s t nm1 and t nm0 i n t he t mnc1 regi ster should be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm output mode, the tncclr bit has no ef fect as the pwm period. both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? 10-bit ptm, pwm output mode ccrp 1~1023 0 pe ? iod 1~10 ? 3 10 ? 4 duty ccra if f sys = 8 mhz, tm clock source select f sys /4, ccrp = 512 and ccra = 128, the ptm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 3.90625 khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%.
rev. 1.60 76 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra tno? tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) ti?e counte? clea?ed ?y ccrp pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high tnm [1:0] = 10 pwm duty cycle set ?y ccra pwm ?esu?es ope?ation output cont?olled ?y othe? pin-sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o/p pin (tnoc=0) pwm output mode (n=0) note: 1. here counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.60 77 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom single pulse output mode to se lect t his m ode, t he r equired b it p airs, t nm1 a nd t nm0 sh ould b e se t t o 1 0 r espectively a nd a lso the corresponding tnio1 and tnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the t rigger fo r t he pu lse ou tput l eading e dge i s a l ow t o hi gh t ransition of t he t non bi t, whi ch can be implement ed using the appli cation program. however in the single pulse output mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse output mode ccrp is not used. the tncclr bit is also not used.

? ? ? ? ? ?? ? ? ?? single pulse generation (n=0)
rev. 1.60 78 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra tno? tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) ti?e counte? stopped ?y ccra pause resu?e counte? stops ?y softwa?e counte? reset when tno? ?etu?ns high tnm [1:0] = 10 ; tnio [1:0] = 11 pulse width set ?y ccra output inve?ts when tnpol = 1 ?o ccrp inte??upts gene?ated tm o/p pin (tnoc=0) tckn pin softwa?e t?igge? clea?ed ?y ccra ?atch tckn pin t?igge? auto. set ?y tckn pin softwa?e t?igge? softwa?e clea? softwa?e t?igge? softwa?e t?igge? single pulse output mode (n=0) note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse output mode, tnio [1:0] must be set to 11 and can not be changed.
rev. 1.60 79 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom capture input mode to s elect this mode bits tnm1 and tnm0 in the tm nc1 regis ter s hould be s et to 01 res pectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tpn _0, tpn_1 or tckn pin, selected by the tncapts bit in the tmnc0 register . the input pin active edge can be eit her a rising edge, a falling edge or both rising and falling edges; the act ive edge transi tion type is sel ected using the tnio1 and tnio0 bit s in t he tmnc1 regist er. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn _0, tpn_1 or tckn pin the present value in the counter will be latched into the ccra register and a tm interrupt generated. irrespective of what events occur on the tpn _0, tpn_1 or tckn pin the counter will continue to free run until the tnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse wi dths. the tnio1 and tnio0 bit s ca n se lect the ac tive tri gger edge on the tpn _0, tpn_1 or tckn pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn _0, tpn_1 or tckn pin, however it must be noted that the counter will continue to run. as the tpn _0, tpn_1 or tckn pin is pin shared with other functions, care must be taken if the tmn is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnoc and tnpol bits are not used in this mode.
rev. 1.60 80 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value yy ccrp tno? tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value ti?e counte? clea?ed ?y ccrp pause resu?e counte? reset tm captu?e pin tpn_x o? tckn xx counte? stop tnio [1:0] value xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disa?le captu?e tnm [1:0] = 01 capture input mode (n=0) note: 1. tnm[1:0] = 01 and active edge set by the tnio[1:0] bits 2. a tm capture input pin active edge transfers counter value to ccra 3. the tncclr bit is not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determin es the counter value and the counter has a maximum count value when ccrp is equal to zero
rev. 1.60 81 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom compact type tm C ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, t imer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one external output pin. name tm no. tm input pin tm output pin 10- ? it ctm 1 ? ?? 3 tck1 ? tck ?? tck3 tp1 ? tp ?? tp3 compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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? - ??? ?? - ? - ? ? ? - ? ?? ? - ? - ? compact type tm block digram (n=1~3)
rev. 1.60 8 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom compact type tm register description overall operat ion of t he compa ct tm i s c ontrolled usi ng si x regi sters. a rea d only regi ster pai r exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. register name bit 7 6 5 4 3 2 1 0 tmnc0 tnpau tnck ? tnck1 tnck0 tno ? tnrp ? tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d3 d ? d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d3 d ? d1 d0 tmnah d9 d8 compact tm register list (n=1~3) tmnc0 register bit 7 6 5 4 3 2 1 0 ? a ? e tnpau tnck ? tnck1 tnck0 tno ? tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f h 010: f h /16 011: f h /64 100: f tbc 101: f tbc 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value w ill be res et to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high.
rev. 1.60 83 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tmnc1 register bit 7 6 5 4 3 2 1 0 ? a ? e tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1, tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1, tnio0 : select tpn output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.60 84 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t nio1 a nd t nio0 bi ts onl y a fter t he t mn ha s be en swi tched of f. unpredictable pwm outputs will occur if the t nio1 and t nio0 bits are changed when the tm is running. bit 3 tnoc : tpn output control bit compare match output mode 0: initial low 1: initial high pwm output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm output mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output m ode it determines the logic level of the tm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm output mode.
rev. 1.60 85 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tmndl register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d5 d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 d9~d8 : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 ? a ? e d7 d6 d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 ? a ? e d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 d9~d8 : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8
rev. 1.60 86 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm output mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs fro m co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.60 87 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3 ff ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ti?e ccrp =0 ccrp > 0 counte? ove?flow ccrp > 0 counte? clea?ed ?y ccrp value pause resu?e stop counte? resta?t tncclr = 0 ; tnm [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag ?ote tnio [1:0 ] = 10 active high output select he?e tnio [1:0 ] = 11 toggle output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol is high compare match output mode - tncclr = 0 (n=1~3) note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.60 88 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value 0x3 ff ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ti?e ccra =0 ccra = 0 counte? ove?flow ccra > 0 counte? clea?ed ?y ccra value pause resu?e stop counte? resta?t tncclr = 1 ; tnm [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag ?ote tnio [1:0 ] = 10 active high output select he?e tnio [1:0 ] = 11 toggle output select output not affected ?y tnaf flag . re?ains high until ?eset ?y tno? ?it output pin reset to initial value output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol is high tnpf not gene?ated ?o tnaf flag gene?ated on ccra ove?flow output does not change compare match output mode - tncclr = 1 (n=1~3) note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.60 89 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fe xible. i n t he pw m ou tput mo de, t he t ncclr b it h as n o e ffect o n t he pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency o r d uty c ycle i s d etermined u sing t he t ndpx b it i n t he t mnc1 r egister. t he pw m waveform f requency a nd d uty c ycle c an t herefore b e c ontrolled b y t he v alues i n t he c cra a nd ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? ctm, pwm output mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod 1 ? 8 ? 56 384 51 ? 640 768 896 10 ? 4 duty ccra if f sys = 8 mhz, tm clock source is f sys /4, ccrp = 100b and ccra = 128, the ctm pwm output frequency = (f sys /4)/512 = f sys /2048 = 3.90625 khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? ctm, pwm output mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b pe ? iod ccra duty 1 ? 8 ? 56 384 51 ? 640 768 896 10 ? 4 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.60 90 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? clea?ed ?y ccrp pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high tndpx = 0 ; tnm [1:0 ] = 10 pwm duty cycle set ?y ccra pwm ?esu?es ope?ation output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccrp tm o / p pin ( tnoc =0) pwm output mode - tndpx = 0 (n=1~3) note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.60 91 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom counte? value ccrp ccra tno? tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc =1) ti?e counte? clea?ed ?y ccra pause resu?e counte? stop if tno? ?it low counte? reset when tno? ?etu?ns high tndpx = 1 ; tnm [1:0 ] = 10 pwm duty cycle set ?y ccrp pwm ?esu?es ope?ation output cont?olled ?y othe? pin - sha?ed function output inve?ts when tnpol = 1 pwm pe?iod set ?y ccra tm o / p pin ( tnoc =0) pwm output mode - tndpx = 1 (n=1~3) note: 1. here tndpx = 1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.60 9 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom analog to digital converter C adc the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. input channels a/d channel select bits input pins 10 acs4 ? acs3~acs0 a ? 0~a ? 9 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers.
? ? ? ? ? ?? ? - -? ? ?? ? ? ? ? ?? ? ? ? ? -? ? ? ? ? ? ? ? ?? ? ? ? ? ? a/d converter structure a/d converter register description overall operation of the a/d converter is controlled using six registers. a read only register pair exists to store the adc data 12-bit value. the remaining four registers are control registers which setup the operating and control function of the a/d converter.
rev. 1.60 93 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom register name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d3 d ? d1 d0 adrl(adrfs=1) d7 d6 d5 d4 d3 d ? d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs3 acs ? acs1 acs0 adcr1 acs4 vbge ? vrefs adck ? adck1 adck0 acerl ace7 ace6 ace5 ace4 ace3 ace ? ace1 ace0 acerh ace9 ace8 a/d converter register list a/d converter data registers C adrl, adrh the de vices, whi ch ha ve a n i nternal 12-bi t a/ d c onverter, re quire t wo da ta re gisters, a hi gh byt e register, kn own a s adrh, a nd a l ow b yte re gister, k nown a s adrl . aft er t he c onversion p rocess takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised , the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl, acerh to c ontrol t he f unction a nd o peration o f t he a/ d c onverter, f our c ontrol r egisters k nown a s adcr0, adcr1 , acerl and acer h are provided. these 8-bi t registers defne functi ons such as t he se lection of whi ch a nalog c hannel i s c onnected t o t he i nternal a/ d c onverter, t he di gitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs3~acs0 bits in the adcr0 register and the acs4 bit in the adcr1 register defne the adc input channel number . as the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter . it is the function of the acs4~acs0 bits to determine which analog channel input pin or internal v bg is actually connected to the internal a/d converter. the acerh and acerl control re gister s cont ain the ace 9 ~ace0 bi ts which determ ine whi ch pins on pb and pe port s are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, cle aring the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in additio n, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.60 94 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom adcr0 register bit 7 6 5 4 3 2 1 0 ? a ? e start eocb adoff adrfs acs3 acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : a/d data format control bit 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 acs3~acs0 : select a/d channel (when acs4 is 0) 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001~1111: an9 these are the a/d channel select control bits. as there is only one internal hardware a/ d converter each of the a/d inputs must be routed to the internal converter using these bits. if the acs4 bit is set high, then the internal bandgap v bg will be routed to the a/d converter.
rev. 1.60 95 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom adcr1 register bit 7 6 5 4 3 2 1 0 ? a ? e acs4 vbge ? vrefs adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : select internal v bg as adc input control 0: disable 1: enable this bi t e nables v bg t o be c onnected t o t he a/ d c onverter. t he v bg en bi t m ust frst have been set to enable the bandgap circuit v bg voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap v bg voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v bgen : internal v bg control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap voltage v bg can be used by the a/d converter . if v bg is not used by the a/d convert er and the l vr/lvd function is disabled then the bandgap reference circuit will be automatically switched of f to conserve power . when v bg is switched on for use by the a/d converter , a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as 0 bit 4 vrefs : selecte adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. when the a/d converter reference voltage is supplied on the external vref pin which is pin-shared with other functions, all of the pin-shared function s except vref on this pin are disabled. bit 3 unimplemented, read as 0 bit 2~0 adck2~adck0 : select adc clock source 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: undefned these three bits are used to select the clock source for the a/d converter.
rev. 1.60 96 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom bandgap reference voltage on/off true table: acs4 vbgen lvr/lvd v bg bandgap reference voltage x 0 ena ? le off to g ? d on x 0 disa ? le off to g ? d off x 1 x on on x: dont ca ? e acerl register bit 7 6 5 4 3 2 1 0 ? a ? e ace7 ace6 ace5 ace4 ace3 ace ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7 : defne pb4 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6 : defne pe6 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5 : defne pe5 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4 : defne pe4 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pb3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pb2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pb1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pb0 is a/d input or not 0: not a/d input 1: a/d input, an0
rev. 1.60 97 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom acerh register bit 7 6 5 4 3 2 1 0 ? a ? e ace9 ace8 r/w r/w r/w por 1 1 bit 7~2 unimplemented, read as 0 bit 1 ace9 : defne pb5 is a/d input or not 0: not a/d input 1: a/d input, an9 bit 0 ace8 : defne pe7 is a/d input or not 0: not a/d input 1: a/d input, an8 a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bi t i n t he adcr0 regi ster i s use d t o i ndicate when t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow to t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f , can be chosen to be either f or a subdivided version of f the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/ d clock source is determined by the system clock f , and by bits adck2~adck0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 1 10b. doing so will give a/d clock p eriods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d clock period which may result in inaccurate a/d conversion values. refer t o t he fol lowing t able for e xamples, wh ere va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period.
rev. 1.60 98 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s 2s 4s 8s 16s* 32s* 64s* undefned ? mhz 500ns 1s 2s 4s 8s 16s* 32s* undefned 4mhz 250ns* 500ns 1s 2s 4s 8s 16s* undefned 8mhz 125ns* 250ns* 500ns 1s 2s 4s 8s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace9~ace0 bits in the acerh and acerl registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of the a /d analog input pins are pin-s hared w ith the p b and p e i/o pins as w ell as other functions. t he ac e 9 ~ace0 bi ts i n t he acerh a nd acerl re gister s , de termine wh ether t he input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace9 ~ace0 bits for its corresponding pin is set high then the pins will be setup to be an a/d converter i nput a nd t he ori ginal pi n func tions di sabled. in t his wa y, pi ns c an be c hanged unde r program c ontrol t o c hange t heir f unction b etween a/ d i nputs a nd o ther f unctions. al l p ull-high resistors, w hich are s etup through regis ter programming, w ill be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pb c or p e c port control register to enable the a/d input as when the ace 9 ~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref .
rev. 1.60 99 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom
? ? ? ? ?? ? a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 registers. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace9~ace0 bits in the acerh and acerl registers. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? ste p 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when t his bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the met hod of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16t adck where t adck is equal to the a/d clock period.
rev. 1.60 100 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom adc ?odule o? start eocb acs4~acs0 off on off on t o??st t adcs a/d sa?pling ti?e t adcs a/d sa?pling ti?e reset a/d conve?sion sta?t of a/d conve?sion t adc a/d conve?sion ti?e t adc a/d conve?sion ti?e 00011b 00010b 00000b 00001b adoff end of a/d conve?sion reset a/d conve?sion end of a/d conve?sion sta?t of a/d conve?sion reset a/d conve?sion powe?-on reset 1. define po?t configu?ation ?. select analog channel sta?t of a/d conve?sion a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device s contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb = (v dd or v ref ) 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.
rev. 1.60 101 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom

? ? ? ? ? ? ?? ? ?
? ideal a/d transfer function a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr a de ; disable adc interrupt mov a , 03h mov adcr1, a ; s elect f sys /8 as a /d c lock a nd s witch o ff v bg clr adoff mov a, 0 fh ; s etup ac erl t o c onfgure p ins a n0~an3 mov acerl, a mov a,00h mov acerh,a mov a , 00h mov adcr0, a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : start_conversion: clr start set start ; r eset a /d clr start ; s tart a /d polling_eoc: sz eocb ; p oll t he a dcr0 r egister e ocb b it t o d etect e nd ; o f a /d c onversion jmp polling_eoc ; c ontinue p olling mov a, a drl ; re ad l ow b yte c onversion re sult v alue mov adrl_buffer, a ; s ave r esult t o us er d efned r egister mov a, a drh ; re ad h igh b yte c onversion re sult v alue mov adrh_buffer, a ; s ave r esult t o us er d efned r egister : jmp start_conversion ; s tart n ext a/ d c onversion
rev. 1.60 10 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom example: using the interrupt method to detect the end of conversion clr a de ; disable adc interrupt mov a , 03h mov adcr1, a ; s elect f sys /8 as a /d c lock a nd s witch o ff v bg clr adoff mov a, 0 fh ; s etup ac erl t o c onfgure p ins a n0~an3 mov acerl, a mov a,00h mov acerh,a mov a , 00h mov adcr0, a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : : start_conversion: clr start set start ; r eset a /d clr start ; s tart a /d clr adf ; c lear a dc i nterrupt re quest f ag set a de ; enable adc interrupt set emi ; e nable gl obal i nterrupt : : ; adc interrupt service routine adc_: mov acc_stack, a ; s ave a cc t o u ser d efned m emory mov a, s tatus mov status_stack, a ; s ave st atus t o us er d efned m emory : : mov a, a drl ; re ad l ow b yte c onversion re sult v alue mov adrl_buffer, a ; s ave r esult t o us er d efned r egister mov a, a drh ; re ad h igh b yte c onversion re sult v alue mov adrh_buffer, a ; s ave r esult t o us er d efned r egister : : exit_isr: mov a, s tatus_stack mov status, a ; restore s tatus f rom u ser d efned m emory mov a, ac c_stack ; r estore a cc fr om u ser d efned m emory clr adf ; c lear a dc i nterrupt f ag reti
rev. 1.60 103 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lcd display memory the devices provide an area of embedded data memory for lcd display . this area is located from 80h to 93h of the ram at sector 1. the memory pointer mp1h is the switch between the ram and the lcd display memory . when the mp1h = 01h, data written into 80h~93h will af fect the lcd display . when the mp1h is written other than 01h, any data written into 80h~93h is meant to access the general purpose data memory. the lcd display memory can be read and written to only by indirect addressing mode using mp1l and mp1 h. w hen d ata i s wr itten i nto t he d isplay d ata a rea, i t i s a utomatically r ead b y t he l cd driver which then generates the corres ponding lcd driving signals. t o turn the display on or of f, a 1 or a 0 is written to the corresponding bit of the display memory , respectively . the fgure illustrates the mapping between the display memory and lcd pattern for the device. ?7 ?6 ?5 ?4 ?3 ?? ?1 ?0 seg0 seg1 seg? 180h 181h seg17 seg18 seg19 19?h 193h com7 com6 com5 com4 com3 com? com1 com0 lcd driver output the output number of the device lcd driver can be 20 4 or 20 8 . the lcd driver is r type only. the lcd clock source is from f sub , which can be either the lxt or lirc oscillator .
rev. 1.60 104 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lcd control register lcdc0 register bit 7 6 5 4 3 2 1 0 ? a ? e lcde ? type dtyc bias rsel ? rsel1 rsel0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 lcden : lcd enable/disable control 0: disable 1: enable note t hat t he l cd dri ver a nd a/ d c onverter shou ld not be e nabled si multaneously when the lcd output and a/d channel are shared with the same pin. bit 6 type : lcd w aveform t ype selection 0: t ype a 1: t ype b bit 5 dtyc : defne lcd duty 0: 1/4 duty ( lcd com: com0~com3) 1: 1/8 duty (lcd com: com0~com7) note: if dtyc=1, then com4~com7 pins will be confgured as lcd com. if dtyc=0, then com4~com7 pins will be confgured as i/o. bit 4 bias : defne lcd bias 0: 1/3 bias 1: 1/4 bias bit 3 unimplemented, read as 0 bit 2~0 rsel2~rsel0 : t otal bias resistor r t selection 000: 1170k 001: 225k 010: 60k 011: quick charging mode, switch between 60k and 1170k. 1xx: quick charging mode, switch between 60k and 225k. note: the bias resistor for 1/3 bias is r t /3, 1/4 bias is r t /4. the de vices pr ovide l ow po wer qu ick c harging m ode fo r l cd di splay. in qu ick c harging m ode, the lcd will provide lcd bias current by r t =60k, at beginning of lcd display refreshes (i.e the moment on lcd com changes). after quick char ging time, the bias resistor will change to 225k/1170k.
rev. 1.60 105 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lcdc1 register bit 7 6 5 4 3 2 1 0 ? a ? e qct ? qct1 qct0 vlcd3 vlcd ? vlcd1 vlcd0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 qct2~qct0 : quick charging time selection 000: 1 t sub 001: 2 t sub 010: 3 t sub 011: 4 t sub 100: 5 t sub 101: 6 t sub 110: 7 t sub 111: 8 t sub t sub = 1/f sub bit 6 ~ 4 unimplemented, read as "0" bit 3 ~ 0 vlcd3~vlcd0 : vlcd selection 0000: 8/16v dd 0001: 9/16v dd 0010: 10/16v dd 0011: 11/16v dd 0100: 12/16v dd 0101: 13/16v dd 0110: 14/16 v dd 0111: 15/16v dd 1000~1111: 16/16v dd
rev. 1.60 106 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom segcr0 register bit 7 6 5 4 3 2 1 0 ? a ? e seg7c seg6c seg5c seg4c seg3c seg ? c seg1c seg0c r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 seg7c : select seg7 or pd7 0: seg7 1: pd7 bit 6 seg6c : select seg6 or pd6 0: seg6 1: pd6 bit 5 seg5c : select seg5 or pd5 0: seg5 1: pd5 bit 4 seg4c : select seg4 or pd4 0: seg4 1: pd4 bit 3 seg3c : select seg3 or pd3 0: seg3 1: pd3 bit 2 seg2c : select seg2 or pd2 0: seg2 1: pd2 bit 1 seg1c : select seg1 or pd1 0: seg1 1: pd1 bit 0 seg0c : select seg0 or pd0 0: seg0 1: pd0
rev. 1.60 107 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom segcr1 register bit 7 6 5 4 3 2 1 0 ? a ? e seg15c seg14c seg13c seg1 ? c seg11c seg10c seg9c seg8c r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 seg15c : select seg15 or pc7 0: seg15 1: pc7 bit 6 seg14c : select seg14 or pc6 0: seg14 1: pc6 bit 5 seg13c : select seg13 or pc5 0: seg13 1: pc5 bit 4 seg12c : select seg12 or pc4 0: seg12 1: pc4 bit 3 seg11c : select seg11 or pc3 0: seg11 1: pc3 bit 2 seg10c : select seg10 or pc2 0: seg10 1: pc2 bit 1 seg9c : select seg9 or pc1 0: seg9 1: pc1 bit 0 seg8c : select seg8 or pc0 0: seg8 1: pc0 segcr2 register bit 7 6 5 4 3 2 1 0 ? a ? e seg19c seg18c seg17c seg16c r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 seg19c : select seg19 or pf7 0: seg19 1: pf7 bit 2 seg18c : select seg18 or pf6 0: seg18 1: pf6 bit 1 seg17c : select seg17 or pf5 0: seg17 1: pf5 bit 0 seg16c : select seg16 or pf4 0: seg16 1: pf4
rev. 1.60 108 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lcd waveform lcd display off mode com0 ~ com3 va all seng?ent outputs normal operation mode com0 com1 com? com3 all seg?ents a?e off com0 side seg?ents a?e o? all seng?ents a?e o? (othe? co??inations a?e o?itted) vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss 1 f?a?e com1 side seg?ents a?e o? com? side seg?ents a?e o? com3 side seg?ents a?e o? com0?1 side seg?ents a?e o? com0?? side seg?ents a?e o? com0?3 side seg?ents a?e o? lcd driver output C type a - 1/4 duty, 1/3 bias note: v a =v lcd , v b =v lcd 2/3 and v c =v lcd 1/3.
rev. 1.60 109 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lcd display off mode com0 ~ com3 va all seng?ent outputs normal operation mode com0 com1 com? com3 all seg?ents a?e off com0 side seg?ents a?e o? all seng?ents a?e o? (othe? co??inations a?e o?itted) vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss 1 f?a?e com1 side seg?ents a?e o? com? side seg?ents a?e o? com3 side seg?ents a?e o? com0?1 side seg?ents a?e o? com0?? side seg?ents a?e o? com0?3 side seg?ents a?e o? lcd driver output C type b - 1/4 duty, 1/3 bias n ote: v a =v lcd , v b =v lcd 2/3 and v c =v lcd 1/3.
rev. 1.60 110 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom com0 com0 state1 (on) state1 (on) state? (off) state? (off) lcd seg?ent lcd seg?ent t lcd vlcd vlcd vss vss vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 com1 com1 vlcd vlcd vss vss com? com? vlcd vlcd vss vss com3 com3 vlcd vlcd vss vss com4 com4 vlcd vlcd vss vss com5 com5 vlcd vlcd vss vss com6 com6 vlcd vlcd vss vss com7 com7 vlcd vlcd vss vss vlcd vlcd vss vss seg n seg n vlcd vlcd vss vss seg n+1 seg n+1 vss vss seg n+? seg n+? vlcd vlcd vss vss seg n+3 seg n+3 vlcd vlcd vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 vlcd x 3/4 vlcd x 3/4 vlcd x ?/4 vlcd x ?/4 vlcd x 1/4 vlcd x 1/4 lcd driver output C type a - 1/8 duty, 1/4 bias
rev. 1.60 111 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom led driver the devices contain an led driver function of fering high current output drive capability which can be used to drive external leds. led driver operation the various i/o pins of devices have a capability of providing led high current drive outputs, as shown in the accompanying table. device led drive pins HT67F488 ht67f489 pd0~pd7 (high sou ? ce cu ?? ent) pe0~pe7 (high sink cu ?? ent) led driver register iohr0 register bit 7 6 5 4 3 2 1 0 ? a ? e iohs31 iohs30 iohs ? 1 iohs ? 0 iohs11 iohs10 iohs01 iohs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 iohr1 register bit 7 6 5 4 3 2 1 0 ? a ? e iohs71 iohs70 iohs61 iohs60 iohs51 iohs50 iohs41 iohs40 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 iohsn[1:0]: i oh capacity selection for pdn (n=0~7) 00: fullly source driving capacity of gpio 01: 1/3 source driving capacity of gpio 10: 1/4 source driving capacity of gpio 11: 1/6 source driving capacity of gpio
rev. 1.60 11 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom uart interface each device contains an integrated full-duplex asynchronous serial communications uar t interface that enables communication with external devices that contain a serial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. the uar t function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. the integrated uart function contains the following features: ? full-duplex, universal asynchronous receiver and t ransmitter (uart) communication ? 8 or 9 bits character length ? even, odd or no parity options ? one or two stop bits ? baud rate generator with 8-bit prescaler ? parity, framing, noise and overrun error detection ? support for interrupt on address detect (last character bit=1) ? transmitter and receiver enabled independently ? 2-byte deep fifo receive data buffer ? transmit and receive multiple interrupt generation sources: ? transmitter empty ? transmitter idle ? receiver full ? receiver overrun ? address mode detect ? rx pin wake-up interrupt
uart data transfer scheme
rev. 1.60 113 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom uart external pin interfacing to communicate with an external serial interface, the internal uar t has two external pins known as tx and rx . the tx pin is the u art trans mitter pin, w hich can be us ed as a general purpos e i/o or other pin-s hared functional pin if the pin is not configured as a u art trans mitter, w hich occurs when the txen bit in the ucr2 control register is equal to zero. similarly , the rx pin is the uart receiver pin, which can also be used as a general purpose i/o or other pin-shared functional pin, if the pin is not confgured as a receiver , which occurs if the rxen bit in the ucr2 register is equal to zero. along with the uar ten bit, the txen and rxen bits, if set, will automatically setup t hese i/ o or ot her pi n-shared func tional pi ns t o t heir re spective t x out put a nd rx i nput conditions and disable any pull-hig h resistor option which may exist on the rx pin. if the tx and rx pins are shared with the lcd outputs and the uar t interface and lcd driver both are enabled simultaneously, the lcd driver has the priority to use the corresponding pins as lcd outputs. uart data transfer scheme the block diagram shows the overall data transfer structure arrangement for the uar t. the actual data t o be t ransmitted from t he mcu i s fi rst t ransferred t o t he t xr re gister by t he a pplication program. the data will then be transferred to the t ransmit shift register from where it will be shifted o ut, l sb fr st, o nto t he t x p in a t a r ate c ontrolled b y t he b aud r ate ge nerator. on ly t he txr register is mapped onto the mcu data memory , the t ransmit shift register is not mapped and is therefore inaccessible to the application program. data to be received by the uar t is accepted on the external rx pin, from where it is shifted in, lsb fi rst, t o t he re ceiver shi ft r egister a t a ra te c ontrolled by t he b aud ra te ge nerator. w hen the shift register is full, the data will then be transferred from the shift register to the internal rxr register, where it is buf fered and can be manipulated by the application program. only the rxr register i s m apped ont o t he mcu da ta me mory, t he re ceiver shift re gister i s not m apped a nd i s therefore inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared register in the data memory . this shared register known as the txr/rxr register is used for both data transmission and data reception. uart status and control registers there are fve control registers associated with the uar t function. the usr, ucr1 and ucr2 registers c ontrol t he o verall f unction o f t he uar t, wh ile t he b rg r egister c ontrols t he b aud r ate. the actua l data to be transmitted and received on the serial interface is managed through the txr/ rxr data registers. register name bit 7 6 5 4 3 2 1 0 usr perr ? f ferr oerr ridle rxif tidle txif ucr1 uarte ? b ? o pre ? prt stops txbrk rx8 tx8 ucr ? txe ? rxe ? brgh adde ? wake rie tiie teie txr/rxr txrx7 txrx6 txrx5 txrx4 txrx3 txrx ? txrx1 txrx0 brg brg7 brg6 brg5 brg4 brg3 brg ? brg1 brg0 uart register list
rev. 1.60 114 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom usr register the usr register is the status register for the uart, which can be read by the program to determine the present status of the uar t. all fags within the usr register are read only . further explanation on each of the fags is given below: bit 7 6 5 4 3 2 1 0 ? a ? e perr ? f ferr oerr ridle rxif tidle txif r/w r r r r r r r r por 0 0 0 0 1 0 1 1 bit 7 perr : parity error fag 0: no parity error is detected 1: parity error is detected the perr fag is the parity error fag. when this read only fag is 0, it indicates a parity error has not been detected. when the fag is 1, it indicates that the parity of the received word is incorrect. this error fag is applicable only if parity mode (odd or even) is selected. the fag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise fag 0: no noise is detected 1: noise is detected the nf fla g is the noise fla g. whe n thi s read only fla g is "0", it indi cates no noise condition. when the fag is "1", it indicates that the uar t has detected noise on the receiver input. the nf fag is set during the same cycle as the rxif fag but will not be set in the case of as overrun. the n f fag can be cleared by a softw are sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 5 ferr : framing error fag 0: no framing error is detected 1: framing error is detected the ferr fag is the framing error fag. when this read only fag is 0, it indicates that t here i s n o f raming e rror. w hen t he fa g i s 1, i t i ndicates t hat a f raming e rror has been detected for the current character . the fag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error fag 0: no overrun error is detected 1: overrun error is detected the oerr fag is the overrun error fag which indicates when the rece iver buf fer has overfowed. when this read only fag is 0, it indicates that there is no overrun error . when the fag is 1, it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register . the fag is cleared by a software sequence, which is a read to the s tatus regis ter u sr follow ed by an acces s to the rx r data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle fag is the receiver status fag. when this read only fag is 0, it indicates that the receiver is between the init ial detection of the start bit and the completion of the s top bit. when the f ag is 1, it indicates that the receiver is idle. betw een the completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart receiver is idle and the rx pin stays in logic high condition.
rev. 1.60 115 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif fag is the receive data register status fag. when this read only fag is 0, it indicates that the rxr read data register is empty . when the fag is 1, it indicates that t he r xr r ead d ata r egister c ontains n ew d ata. w hen t he c ontents o f t he sh ift register are trans ferred to the rx r register , an interrupt is generated if rie=1 in the ucr2 register . if one or more errors are detected in the received word, the appropriate receive-related fags nf , ferr, and/or perr are set within the same clock cycle. the rxif fag is clear ed when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : t ransmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only fag i s 0, i t i ndicates t hat a t ransmission i s i n p rogress. t his fa g wi ll b e se t t o 1 when the txif fag is 1 and when there is no transmit data or break character being transmitted. when tidle is equal to 1, the tx pin becomes idle with the pin state in logic high condition. the tidle fag is cleared by reading the usr register with tidle set and then writing to the txr register . the fag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : t ransmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif fag is the transmit data register empty fag. when this read only fag is 0, it indicat es that the character is not transferred to the transmitter shift register . when the fag is 1, it indicates that the transmitter shift register has received a character from the txr data register . the txif flag is cleared by reading the uar t status register (usr) with txif set and then writing to the txr data register . note that when t he t xen b it i s se t, t he t xif fa g b it wi ll a lso b e se t si nce t he t ransmit d ata register is not yet full.
rev. 1.60 116 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the various options for the uar t function, such as overall on/of f control, parity control, data transfer bit length etc. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 ? a ? e uarte ? b ? o pre ? prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por 0 0 0 0 0 0 x 0 x unknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are as i/o or other pin-shared functional pins 1: enable uart. tx and rx pins function as uart pins the uar ten bit is the uar t enable bit. if the tx and rx pins are shared with the lcd o utputs a nd t he uar t i nterface a nd l cd d river a re b oth e nabled si multaneously, the l cd dri ver wi ll ha ve t he pri ority t o use t he c orresponding pi ns a s l cd out puts. when this bit is equal to 0, the uar t will be disabled and the rx pin as well as the tx pin will be as general purpose i/o or other pin-shared functional pins. when the bit is equal to 1, the uar t will be enabled and the tx and rx pins will function as defned by the txen and rxen enable control bits. when the uar t is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. in addition, the value of the baud rate counter will be reset. if the uar t is disabled, all error and status fags will be reset. also the txen, rxen, txbrk, rxif , oerr, ferr, perr and nf bits will be cle ared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaf fected. if the uar t is active and the uar ten bit is cleared, all pending transmis sions and receptions will be terminated and the module will be reset as defined above. when the uar t is re-enabled, it will restart in the same confguration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to 1, a 9-bit data length format will be selected. if the bit is equal to 0, then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to 1, the parity function will be enabled. if the bit is equal to 0, then the parity function will be disabled. replace the most signifcant bit position with a parity bit. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to 1, odd parity type will be selected. if the bit is equal to 0, then even parity type will be selected. bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: t wo stop bits format is used this bit determine s if one or two stop bits are to be used. when this bit is equal to 1, two stop bits are used. if this bit is equal to 0, then only one stop bit is used.
rev. 1.60 117 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom bit 2 txbrk : t ransmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the t ransmit break character bit. when this bit is 0, there are no break characte rs and the tx pin operates normally . when the bit is 1, there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to 1, after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 tx8 : t ransmit data bit 8 for 9-bit data transfer format (write only) this bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will st ore t he 9 th b it o f t he t ransmitted d ata k nown a s t x8. t he b no b it i s u sed t o determine whether data transfers are in 8-bit or 9-bit format. ucr2 register the ucr2 register is the second of the two uart control registers and serves several purposes. one of its main functio ns is to control the basic enable/disable operation of the uar t t ransmitter and receiver as well as enabling the various uar t interrupt sources. the register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. further explanation on each of the bits is given below: bit 7 6 5 4 3 2 1 0 ? a ? e txe ? rxe ? brgh adde ? wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 txen : uart t ransmitter enabled control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the t ransmitter enable bit. when this bit is equal to 0, the transmitter will be disabled with any pending data transmissions being aborted. in addition the buf fers will be reset. in this situation the tx pin will be used as an i/o or other pin-shared functional pin. if the txen bit is equal to 1 and the uar ten bit is also equal to 1, the transmitter will be enabled and the tx pin will be controlled by the uar t. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . if this situation occurs, the tx pin will be used as an i/o or other pin-shared functional pin. bit 6 rxen : uart receiver enabled control 0: uart receiver is disabled 1: uart receiver is enabled the bit named rxen is the receiver enable bit. when this bit is equal to 0, the receiver will be disabled with any pending data receptions being aborted. in addition the receive buf fers will be reset. in this situation the rx pin will be used as an i/o or other pin-shared functional pin. if the rxen bit is equal to 1 and the uar ten bit is also equal to 1, the receiver will be enabled and the rx pin will be controlled by the uar t. cleari ng the rxen bit during a reception will cause the data reception to be aborted and will reset the receiv er. if this situation occurs, the rx pin will be used as an i/o or other pin-shared functional pin.
rev. 1.60 118 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator . this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uar t. if this bit is equal to 1, the high speed mode is selected. if the bit is equal to 0, the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detect function is disabled 1: address detect function is enabled the bi t na med adde n i s t he a ddress de tect fu nction e nable c ontrol bi t. w hen t his bit is equal to 1, the address detect function is enabled. when it occurs, if the 8th bit, which corresponds to rx7 if bno=0 or the 9th bit, which corresponds to rx8 if bno=1, ha s a va lue of 1, t hen t he re ceived word wi ll be i dentifed a s a n a ddress, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit d epending o n t he v alue o f b no. i f t he a ddress b it k nown a s t he 8 th o r 9 th b it o f t he received word is 0 with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. bit 3 wake : rx pin falling edge wake-up function enable control 0: rx pin wake-up function is disabled 1: rx pin wake-up function is enabled this bi t e nables or di sables t he re ceiver wa ke-up func tion. if t his bi t i s e qual t o 1 and t he mcu i s i n t he sl eep m ode, a fa lling e dge on t he rx i nput pi n wi ll wa ke- up the device. please reference the uar t rx pin wake-up functions in dif ferent operating mode for the detail. if this bit is equal to 0 and the mcu is in the sleep mode, any edge transitions on the rx pin will not wake-up the device. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the rece iver interrupt. if this bit is equal to 1 and when the receiver overrun fag oerr or receive data available fag rxif is set, the uar t interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the oerr or rxif fags. bit 1 tiie : t ransmitter idle interrupt enable control 0: t ransmitter idle interrupt is disabled 1: t ransmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to 1 and when t he t ransmitter i dle fa g t idle i s se t, due t o a t ransmitter i dle c ondition, t he uart interrupt request fag will be set. if this bit is equal to 0, the uar t interrupt request fag will not be infuenced by the condition of the tidle fag. bit 0 teie : t ransmitter empty interrupt enable control 0: t ransmitter empty interrupt is disabled 1: t ransmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 and when the transmitter empty fag txif is set, due to a transmitter empty condition, the uar t interrupt re quest fl ag will be set. if this bi t is equal to 0 , the uar t interrupt request fag will not be infuenced by the condition of the txif fag.
rev. 1.60 119 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom txr/rxr register bit 7 6 5 4 3 2 1 0 ? a ? e txrx7 txrx6 txrx5 txrx4 txrx3 txrx ? txrx1 txrx0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 txrx7~txrx0 : uart t ransmit/receive data bit 7 ~ bit 0 brg register bit 7 6 5 4 3 2 1 0 ? a ? e brg7 brg6 brg5 brg4 brg3 brg ? brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 brg7~brg0 : baud rate values by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. note: baud rate= f sys /[64(n+1)] if brgh=0 . baud rate= f sys /[16(n+1)] if brgh=1 . baud rate generator to setup the speed of the serial data communication, the uar t function contains its own dedicated baud ra te ge nerator. t he ba ud ra te i s c ontrolled by i ts own i nternal fre e runni ng 8-bi t t imer, t he period of which is determined by two factors. the frst of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. the value n in the brg register which is used in the following baud rate calculation formula determines the division factor . note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) f sys / [64 ( ? +1)] f sys / [16 ( ? +1)] by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register , the required baud rate can be setup. note that because the actual baud rate is determ ined using a discrete value, n, placed in the brg register , there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated.
rev. 1.60 1 ? 0 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom calculating the register and error values for a clock frequency of 4 mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800 . from the above table the desired baud rate br = f sys / [64 (n+1)] re-arranging this equation gives n = [f sys / (br64)] - 1 giving a value for n = [ 4 000000 / (480064) ] - 1 = 12.0208 to obtain the closest value, a decim al value of 12 should be placed into the brg register . this gives an actual or calculated baud rate value of br = 4 000000 / [64(12 + 1)] = 4808 therefore the error is equal to ( 4808 - 48 00) / 48 00 = 0.16% the following table shows actual values of baud rate and error values for the two values of brgh. baud rate k/bps f sys =8mhz baud rates for brgh=0 baud rates for brgh=1 brg kbaud error (%) brg kbaud error (%) 0.3 1. ? 103 1. ? 0 ? 0.16 ? .4 51 ? .404 0.16 ? 07 ? .404 0.16 4.8 ? 5 4.808 0.16 103 4.808 0.16 9.6 1 ? 9.615 0.16 51 9.615 0.16 19. ? 6 17.8857 -6.99 ? 5 19. ? 31 0.16 38.4 ? 41.667 8.51 1 ? 38.46 ? 0.16 57.6 1 6 ? .500 8.51 8 55.556 -3.55 115. ? 0 1 ? 5 8.51 3 1 ? 5 8.51 ? 50 1 ? 50 0 baud rates and error values uart setup and control for data transfer , the uar t functio n utilizes a non-return-to-zero, more commonly known as nrz, format. this is composed of one start bit, eight or nine data bits, and one or two stop bits. parity is supported by the uar t hardware, and can be setup to be even, odd or no parity . for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setti ng, which is the setting at power -on. the number of data bits and stop bits, along with t he pa rity, a re se tup by pr ogramming t he c orresponding b no, pr t, pr en, a nd st ops bi ts in the ucr1 register . the baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received lsb frst. although the uar t transmitter and receiver are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission.
rev. 1.60 1 ? 1 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom enabling/disabling the uart the basic on/of f function of the internal uar t function is controlled using the uar ten bit in the ucr1 register . if the uar ten, txen and rxen bits are set, then these two uar t pins will act as n ormal t x o utput p in a nd r x i nput p in r espectively. i f n o d ata i s b eing t ransmitted o n t he t x pin, then it will default to a logic high value. clearing the uar ten bit will disable the tx and rx pins and allow these two pins to be used as normal i/o or other pin-shared functional pins. when the uar t functi on is disabled the buf fer will be reset to an empty condition, at the same time discarding any remai ning residual data. disabling the uar t will also reset the error and status fags with bits txen, rxen, txbrk, rxif , oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the remaining control bits in the ucr1, ucr2 and brg registers will remain unaf fected. if the uar ten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediate ly suspended and the uar t will be reset to a condition as defned above. if the uart is then subsequently re-enabled, it will restart again in the same confguration. data, parity and stop bit selection the f ormat o f t he d ata t o b e t ransferred i s c omposed o f v arious f actors su ch a s d ata b it l ength, parity on/of f, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register . the bno bit controls the number of data bits which can be set to either 8 or 9, the pr t bit controls the choice of odd or even parity , the pren bit controls the parity on/of f function and the st ops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address bit identifes the frame as an address character . the number of stop bits, which can be either one or two, is independent of the data length. start bit data bits address bits parity bits stop bit example of 8-bit data formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 example of 9-bit data formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats.

rev. 1.60 1 ?? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register . at the transmitter core lies the transmitter shift register , more commonly known as the tsr, whose data is obtained from the transmit d ata r egister, wh ich i s k nown a s t he t xr r egister. t he d ata t o b e t ransmitted i s l oaded into this txr register by the applic ation program. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been transmitted, the tsr can then be loaded with new data from the txr register , if it is available. it should be noted that the tsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmission of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator ha s defned a shi ft c lock sourc e. however , t he t ransmission c an a lso be i nitiated by frst loading data into the txr register , after which the txen bit can be set. when a transmission of data begins, the tsr is normally empty , in which case a transfer to the txr register will result in an immed iate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will i mmediately c ease a nd t he t ransmitter wi ll b e r eset. t he t x output p in wi ll t hen r eturn t o t he i /o or other pin-shared function. transmitting data when the uar t is transmitting data, the data is shifted on the tx pin from the shift register , with the leas t s ignificant bit firs t. in the trans mit mode, the tx r regis ter forms a buf fer betw een the internal bus and the transmitter shift register . it should be noted that if 9-bit data format has been selected, then the msb will be take n from the tx8 bit in the ucr1 register . the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of the bno, pr t, pren and st ops bits to defne the required word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the txen bit to ensure that the tx pin is used as a uart transmitter pin. ? access the usr register and write the data that is to be transmitted into the txr register . note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be inhibited from being written to the txr register . clearing the txif fag is always achieved using the following software sequence: ? a usr register access ? a txr register write execution the read-only txif fag is set by the uar t hardware and if set indic ates that the txr register is empty and that other data can now be written into the txr register without overwriting the previous data. if the teie bit is set then the txif fag will generate an interrupt.
rev. 1.60 1 ? 3 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom during a data transmission, a write instruction to the txr register will place the data into the txr register, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register , resulting in the commencement of data transmission, and the txif bit being immediately se t. w hen a fra me t ransmission i s c omplete, whi ch ha ppens a fter st op bi ts a re se nt or after the break frame, the tidle bit will be set. t o clear the tidle bit the following software sequence is used: ? a usr register access ? a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmit break if the txbrk bit is set then break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13n 0 bits and stop bits, where n=1, 2, etc. if a break character is to be transmitted then the txbrk bit must be frst set by the application program, then c leared t o gene rate t he st op bit s. t ransmitting a brea k cha racter wi ll not gene rate a t ransmit interrupt. note that a break condition length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will fnish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. uart receiver the uar t is capable of receiving word lengths of either 8 or 9 bits. if the bno bit is set, the word length will be set to 9 bits with the msb being stored in the rx8 bit of the ucr1 register . at the receiver core lies the receive serial shift register , commonly known as the rsr. the data which is receive d on the rx external input pin, is sent to the data recovery block. the data recovery block operating speed is 16 times that of the baud rate, while the main receiv e serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the receive data register, if the register is empty. the data which is received on the external rx input pin is sample d three times by a majority detect circuit to determine the logic level that has been placed onto the rx pin. it should be noted that the rsr register , unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uar t receiver is receiv ing data, the data is serially shifted in on the external rx input pin, lsb frst. in the read mode, the rxr register forms a buf fer between the internal bus and the receiver shift register . the rxr register is a two byte deep fifo data buf fer, where two bytes can be held in the fifo while a third byte can continue to be received. note that the application program must e nsure t hat t he d ata i s r ead f rom r xr b efore t he t hird b yte h as b een c ompletely sh ifted in, o therwise t his t hird b yte wi ll b e d iscarded a nd a n o verrun e rror oe rr wi ll b e su bsequently indicated. the steps to initiate a data transfer can be summarized as follows: ? make the correct selection of bno, pr t, pren and st ops bits to defne the word length, parity type and number of stop bits. ? setup the brg register to select the desired baud rate. ? set the rxen bit to ensure that the rx pin is used as a uart receiver pin.
rev. 1.60 1 ? 4 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom at this point the receiver will be enabled which will begin to look for a start bit. when a character is received the following sequence of events will occur: ? the rxif bit in the usr register will be set when rxr register has data available, at least one more character can be read. ? when the contents of the shift register have been transferred to the rxr register , then if the rie bit is set, an interrupt will be generated. ? if during reception, a frame error , noise error , parity error , or an overrun error has been detected, then the error fags can be set. the rxif bit can be cleared using the following software sequence: ? a usr register access ? an rxr register read execution receive break any break character received by the uar t will be managed as a framing error . the receiver will count and expect a certain number of bit times as specifed by the value s programmed into the bno and st ops bits. if the break is much longer than 13 bit times, the reception will be considered as complete a fter t he num ber of bi t t imes spe cifed by bno a nd st ops. t he rxif bi t i s se t, fe rr is set, zeros are loaded into the rece ive data register , interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the ferr fag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the ass umption that the break condition on the line is the next start bit. a break is regarded as a character that contains only zeros with the ferr fag set. the break character will be loaded into the buf fer and no further data will be received until stop bits are received. it should be noted that the ridle read only fag will go high when the stop bits have not yet been received. the reception of a break character on the uar t registers will result in the following: ? the framing error fag, ferr, will be set. ? the receive data register, rxr, will be cleared. ? the oerr, nf, perr, ridle or rxif fags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status fag in the usr register , otherwise known as the ridle fag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle fag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt fag rxif in the usr register is set by an edge generated by the receiver. an i nterrupt i s ge nerated i f rie =1, whe n a word i s t ransferred from t he re ceive shi ft register, rsr, to the receive data register , rxr. an overrun error can also generate an interrupt if rie=1.
rev. 1.60 1 ? 5 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom managing receiver errors several types of reception errors can occur within the uart module, the following section describes the various types and how they are managed by the uart. overrun error C oerr flag the rxr register is composed of a two byte deep fifo data buf fer, where two bytes can be held in the fifo register , while a third byte can continue to be received. before this third byte has been entirely shifted in, the data should be read from the rxr register . if this is not done, the overrun error fag oerr will be consequently indicated. in the event of an overrun error occurring, the following will happen: ? the oerr fag in the usr register will be set. ? the rxr contents will not be lost. ? the shift register will be overwritten. ? an interrupt will be generated if the rie bit is set. the o err flag can be cleared by an acces s to the u sr regis ter follow ed by a read to the rx r register. noise error C nf flag over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. i f n oise i s detected within a frame the following will occur: ? the read only noise fag, nf, in the usr register will be set on the rising edge of the rxif bit. ? data will be transferred from the shift register to the rxr register. ? no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note t hat t he nf fa g i s r eset b y a usr r egister r ead o peration f ollowed b y a n r xr r egister r ead operation. framing error C ferr flag the read only framing error fag, ferr, in the usr register , is set if a zero is detected instead of stop bits. if two stop bits are selecte d, both stop bits must be high, otherwise the ferr fag will be set. the ferr fag is buffered along with the received data and is cleared on any reset. parity error C perr flag the read only parity error fag, perr, in the usr register , is set if the parity of the received word is incorrect. this error fag is only applicable if the parity is enabled, pren = 1, and if the parity type, odd or even is selected. the read only perr fag is buf fered along with the received data bytes. it is cleared on any reset. it should be noted that the ferr and perr fags are buf fered along with the corresponding word and should be read before reading the data word.
rev. 1.60 1 ? 6 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom uart module interrupt structure several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt cont rol is enabled and the stac k is not ful l, the progra m wil l jump to it s corresponding interrupt vector w here it can be serviced before returning to the main program. four of thes e conditions h ave t he c orresponding usr r egister fa gs wh ich wi ll g enerate a uar t i nterrupt i f i ts associated interrupt enable control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address det ect condit ion, whi ch i s al so a uar t i nterrupt source, does not have an associa ted flag, but will generate a uar t interrupt when an address detect condition occurs if its function is e nabled by se tting t he adde n bi t i n t he ucr2 re gister. an rx pi n wa ke-up, whi ch i s a lso a uart interrupt source, does not have an associated fag, but will generate a uar t interrupt if the microcontroller is woken up by a falling edge on the rx pin, if the w ake and rie bits in the ucr register are set. note that in the event of an rx wake-up interrupt occurring, there will be a certain period of delay , commonly known as the system start-up t ime, for the oscillator to restart and stabilize before the system resumes normal operation. note t hat t he usr r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. the flags will be cleared automatically whe n c ertain a ctions a re t aken by t he uar t, t he de tails of whi ch a re gi ven i n t he uart regi ster se ction. the overal l uar t i nterrupt ca n be disable d or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed. t?ans?itte? e?pty flag txif usr registe? t?ans?itte? idle flag tidle receive? ove??un flag oerr receive? data availa?le rxif adde? rx pin wake-up wake 0 1 0 1 0 1 rx7 if b?o=0 rx8 if b?o=1 ucr? registe? or rie 0 1 tiie 0 1 teie 0 1 uart inte??upt request flag uarf ucr? registe? uare i?tc? registe? emi i?tc0 registe? uart interrupt scheme
rev. 1.60 1 ? 7 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom address detect mode setting the address detect mode bit, adden, in the ucr2 register , enables this special mode. if this bit is enabled then an additional qualifer will be placed on the generation of a receiver data available interrup t, which is requested by the rxif fag. if the adden bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. note that the mf e, u re and em i interrupt enable bits mus t also be enabled for correct interrupt generation. this highes t addres s bit is the 9th bit if bn o=1 or the 8th bit if bn o=0. if this bit is high, then the received word will be defined as an address rather than data. a data a vailable interrupt will be generated every time the last bit of the received word is set. if the adden bit is not enabled, then a receiver data a vailable interrupt will be generated each time the rx if flag i s se t, i rrespective o f t he d ata l ast b it st atus. t he a ddress d etect m ode a nd p arity e nable a re mutually exclusive functions. therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0 1 adden bit function uart module power down and wake-up when the mcu is in the power down mode, the uar t will cease to function. when the device enters the power down mode, all clock sources to the module are shutdown. if the mcu enters the power down mode while a transmission is still in progress, then the transmission will be paused until the uar t clock source derived from the microcontroller is activated. in a similar way , if the mcu enters the power down mode while receiving data, then the reception of data will likewise be paused. when the mcu enters the power down mode, note that the usr, ucr1, ucr2, transmit and receive registers, as well as the brg register will not be af fected. it is recommended to make sure frst that the uar t data transmission or reception has been fnished before the microcontroller enters the power down mode. the ua rt function contains a receiver rx pin wake-up function, which is enabled or disabled by the w ake bit in the ucr2 register . if this bit, along with the uar t enable bit, uar ten, the receiver enable bit, rxen and the receiver interrupt bit, rie, are all set before the mcu enters the power down mode, then a falli ng edge on the rx pin will wake up the mcu from the power down mode . note that as it t akes certa in system cl ock cycl es after a wake-up, before norma l microcontroller operation resumes, any data received during this time on the rx pin will be ignored. for a uar t wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, emi, and the uar t interrupt enable bit, ure, must also be set. if these two bits are not set then only a wake up event will occur and no interrupt will be generated. note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the uart interrupt will not be generated until after this time has elapsed. below table illustrates the uart rx wake-up functions in different operating mode.
rev. 1.60 1 ? 8 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom operation mode description rx wake-up function cpu f sys f h f sub idle0 mode off off off on when the cpu ente ? s the idle0 ? ode ? a falling edge on the rx pin will not tu ? n on the f sys clock and not wake up the cpu even if ucr ? . ? (rie)=1 and ucr ? .3(wake)=1. idle1 mode off on on on when the ucr ? . ? (rie)=1 ? ucr ? .3(wake)=1 and the cpu is ente ? ed in idle1 ? ode: 1. if the uart is not t ? ansfe ? and a falling edge occu ?? ed on the rx pin ? this will tu ? n on f sys and cpu is still off. if the uart t ? ans ? ission is on going ? cpu will ? e woken up in the end of t ? ansfe ? . ? . if the uart t ? ans ? ission is on going ? the cpu will ? e woken up in the end of t ? ansfe ? . ? ote: if rie=0 ? w ake=1 and the uart t ? ans ? ission is on going ? t he cpu will not ? e woken up in the end of ? eceive. idle1 mode off on (f sys =f h ~f h /64) on off when the ucr ? . ? (rie)=1 ? ucr ? .3(wake)=1 and the cpu is ente ? ed in idle 1 ? ode: 1. if the uart is not t ? ansfe ? and a falling edge occu ?? ed on the rx pin ? this will tu ? n on f sys and cpu is still off. if the uart t ? ans ? ission is on going ? cpu will ? e woken up in the end of t ? ansfe ? . ? . if the uart t ? ans ? ission is on going ? the cpu will ? e woken up in the end of t ? ansfe ? . ? ote: if rie=0 ? w ake=1 and the uart t ? ans ? ission is on going ? t he cpu will not ? e woken up in the end of ? eceive. sleep0/1 mode off off off on/off when the ucr ? . ? (rie)=1 ? ucr ? .3(wake)=1 and the cpu is ente ? ed in sleep ? ode ? a falling edge on the rx pin will tu ? n on f sys and wake-up cpu.
rev. 1.60 1 ? 9 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int0~int3 pins, while the internal interrupts are generated by various internal functions such as tms, t ime base, lvd, eeprom, uart and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the frst is the intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi4 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/ disable bit or f for request f ag. function enable bit request flag notes glo ? al emi i ? tn pin i ? tne i ? tnf n=0~3 a/d conve ? te ? ade adf multi-function mfne mfnf n=0~4 ti ? e base tbne tbnf n=0 o ? 1 lvd lve lvf eeprom dee def uart uare uarf tm tnpe tnpf n=0~3 tnae tnaf n=0~3 note: the eeprom interrupt is only for the ht67f489. interrupt register bit naming conventions register name bit 7 6 5 4 3 2 1 0 i ? teg i ? t3s1 i ? t3s0 i ? t ? s1 i ? t ? s0 i ? t1s1 i ? t1s0 i ? t0s1 i ? t0s0 i ? tc0 mf0f i ? t1f i ? t0f mf0e i ? t1e i ? t0e emi i ? tc1 adf mf3f mf ? f mf1f ade mf3e mf ? e mf1e i ? tc ? mf4f i ? t3f i ? t ? f uarf mf4e i ? t3e i ? t ? e uare mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi ? t ? af t ? pf t ? ae t ? pe mfi3 t3af t3pf t3ae t3pe mfi4 tb1f tb0f def lvf tb1e tb0e dee lve note: the eeprom interrupt is only for the ht67f489. interrupt register contents
rev. 1.60 130 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom integ register bit 7 6 5 4 3 2 1 0 ? a ? e i ? t3s1 i ? t3s0 i ? t ? s1 i ? t ? s0 i ? t1s1 i ? t1s0 i ? t0s1 i ? t0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 int3s1~int3s0 : interrupt edge control for int3 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges bit 5~4 int2s1~int2s0 : interrupt edge control for int2 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges
rev. 1.60 131 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom intc0 register bit 7 6 5 4 3 2 1 0 ? a ? e mf0f i ? t1f i ? t0f mf0e i ? t1e i ? t0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request flag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request flag 0: no request 1: interrupt request bit 3 mf0e : multi-function 0 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.60 13 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom intc1 register bit 7 6 5 4 3 2 1 0 ? a ? e adf mf3f mf ? f mf1f ade mf3e mf ? e mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 6 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 mf3e : multi-function 3 interrupt control 0: disable 1: enable bit 1 mf2e : multi-function 2 interrupt control 0: disable 1: enable bit 0 mf1e : multi-function 1 interrupt control 0: disable 1: enable
rev. 1.60 133 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom intc2 register bit 7 6 5 4 3 2 1 0 ? a ? e mf4f i ? t3f i ? t ? f uarf mf4e i ? t3e i ? t ? e uare r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf4f : multi-function interrupt 4 request flag 0: no request 1: interrupt request bit 6 int3f : int3 pin interrupt request fag 0: no request 1: interrupt request bit 5 int2f : int2 pin interrupt request fag 0: no request 1: interrupt request bit 4 uarf : uart interrupt request fag 0: no request 1: interrupt request bit 3 mf4e : multi-function 4 interrupt control 0: disable 1: enable bit 2 int3e : int3 pin interrupt control 0: disable 1: enable bit 1 int2e : int2 pin interrupt control 0: disable 1: enable bit 0 uare : uart interrupt control 0: disable 1: enable
rev. 1.60 134 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom mfi0 register bit 7 6 5 4 3 2 1 0 ? a ? e t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 ? a ? e t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.60 135 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom mfi2 register bit 7 6 5 4 3 2 1 0 ? a ? e t ? af t ? pf t ? ae t ? pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable mfi3 register bit 7 6 5 4 3 2 1 0 ? a ? e t3af t3pf t3ae t3pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t3af : tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t3pf : tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t3ae : tm3 comparator a match interrupt control 0: disable 1: enable bit 0 t3pe : tm3 comparator p match interrupt control 0: disable 1: enable
rev. 1.60 136 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom mfi4 register bit 7 6 5 4 3 2 1 0 ? a ? e tb1f tb0f def lvf tb1e tb0e dee lve r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f : t ime base 1 interrupt request flag 0: no request 1: interrupt request bit 6 tb0f : t ime base 0 interrupt request flag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable note: the eeprom interrupt is only for the ht67f489.
rev. 1.60 137 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom interrupt operation when the conditio ns for an interrupt event occur , such as a tm comparator p , comparator a match or a/d conversion completion etc, the relevant interrupt request f ag will be set. whether the request f ag actually generates a program jump to the relevant interrupt vector is determined by the condition of t he i nterrupt e nable bi t. if t he e nable bi t i s se t hi gh t hen t he progra m wi ll j ump t o i ts re levant vector, if the enable bit is zero then although the interrupt request f ag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying di agrams with their order of priority . som e interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request f ag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest f ags wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding f ag should be set before the device is in sleep or idle mode.
rev. 1.60 138 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom 04h 0ch 10h 1ch vector low p ? io ? ity high request flags ena ? le bits maste ? ena ? le request flags ena ? le bits emi auto disa ? led in isr inte ?? upt ? a? e inte ?? upt ? a? e emi emi emi emi t1af tm1 a t1ae t1pf tm1 p t1pe i? t 0f i? t 0 pin i? t 0e mf0f m. funct. 0 mf0e mf1f m. funct. 1 mf1e adf a/d ade xxf legend request flag C no auto ? eset in isr xxf request flag C auto ? eset in isr xxe ena ? le bit t0af tm0 a t0pf tm0 p t0ae t0pe ?8h emi i ? t3f i ? t3 pin i ? t3e 18h emi mf 3f m. funct. 3 mf 3e ?0h emi uar f uart uar e 08h emi i ? t1f i ? t1 pin i ? t1e 14h emi t ? af tm ? a t ? ae t ? pf tm ? p t ? pe mf ?f m. funct. ? mf ?e t3 af tm 3 a t3 ae t3 pf tm 3 p t3 pe ?4h emi i ? t ?f i ? t ? pin i ? t ?e ? ch emi def eeprom dee lvf lvd lve mf4f m. funct. 4 mf4e tb1 f ti ? e base 1 tb1 e tb0f ti ? e base 0 tb0e inte ?? upts contained within multi - function inte ?? upts ht67f489 only interrupt structure
rev. 1.60 139 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom external interrupt the external interrupt is controlled by signal transitions on the intn pins. an external interrupt request will take place when the external interrupt request f ag, intnf , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, intne, must frst be set. additionally the correc t i nterrupt edge t ype must be se lected usi ng t he int eg regi ster t o ena ble t he ext ernal interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-shared with i/o pin, it can only be confgured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector will take place. when the interrupt is serviced, the external interrupt request f ag, intnf, wi ll b e a utomatically r eset a nd t he e mi b it wi ll b e a utomatically c leared t o d isable o ther interrupts. note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi-function interrupt within these devices there are up to four multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sourc es, na mely t he t m int errupts, l vd i nterrupt, e eprom i nterrupt a nd t ime ba se interrupt. a multi-function interrupt request will take place the multi-function interrupt request f ag, mfnf is set. the mul ti-function interrupt fag will be set when any of its included func tions generat e an interrupt request f ag. t o allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained w ithin each of m ulti-function interrupt occurs , a s ubroutine call to the m ulti-function interrupt vector will take place. when the interrupt is serviced, the related multi-function request fag, mfnf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt f ags wi ll be a utomatically reset when the interrupt is serviced, the request f ags from the original source of the multi-function interrupts, namely the tm interrupts , l vd interrupt, eep rom interrupt and t ime base interrupt, will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request f ag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.60 140 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom uart interrupt several i ndividual uar t c onditions c an ge nerate a uar t i nterrupt. w hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . these conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an rx pin wake-up. t o allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, emi, and uar t interrupt enable bit, uare, must frst be set. when the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the uar t interrupt vector will take place. when the interrupt is serviced, the uart interrupt fag, uarf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. however , the usr register fags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart section. time base interrupt the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program t o b ranch t o t heir r espective i nterrupt v ector a ddresses, t he g lobal i nterrupt e nable b it, emi and t ime base enable bits, tb0e or tb1e, and associated multi-function interrupt enable bit, must frst be set. when the interrup t is enabled, the stack is not full and the t ime base overfows, a subroutine call to the multi-function interrupt vector will take place. when the t ime base interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared . as the tb0f or tb1f fag will not be automatically cleared, it has to be cleared by the application program. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.
rev. 1.60 141 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tbc register bit 7 6 5 4 3 2 1 0 ? a ? e tbo ? tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb1 1, tb10 : select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 unimplemented, read as 0 bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb

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time base interrupt eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def , is set, which occurs when an eeprom w rite cycl e ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack i s n ot f ull a nd a n e eprom w rite c ycle e nds, a su broutine c all t o t he r espective e eprom interrupt vector will take place. when the eeprom interrupt is serviced, the emi bit will be automatically clea red to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.60 14 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi -function interrupt vector will take place. when the low v oltage interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, however only t he mul ti-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the com pact a nd pe riodic t ype t ms ha ve t wo i nterrupts e ach. al l of t he t m i nterrupts a re contained w ithin the multi-function interrupts. for each of the compact and periodic t ype tm s there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request f ag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt f ag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request f ag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function.
rev. 1.60 143 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request f ag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request f ag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request f ag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.60 144 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom low voltage detector C lvd each device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a l ow vo ltage c ondition wi ll be de termined. a l ow vo ltage c ondition i s i ndicated whe n t he l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 ? a ? e lvdo lvde ? vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 lvden : low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 vlvd2~vlvd0 : select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.60 145 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lvd operation the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interru pt to be generated if v dd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. when l vd functi on is enabled, it is recommenced to clear l vd fag frst, and then enables interrupt function to avoid mistake action.
rev. 1.60 146 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options 1 high speed syste ? oscillato ? selection f h C hxt o ? hirc application circuits

rev. 1.60 147 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.60 148 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction set . as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been c arried out. t his i s done by pl acing a re turn i nstruction ret i n t he subrout ine whi ch wi ll cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. howeve r, whe n working wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.60 149 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom instruction set summary the i nstructions re lated t o t he da ta m emory a ccess i n t he fol lowing t able c an be used whe n t he desired data memory is located in data memory sector 0. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] add data me ? o ? y to acc 1 z ? c ? ac ? ov ? sc addm a ? [ ? ] add acc to data me ? o ? y 1 ? ote z ? c ? ac ? ov ? sc add a ? x add i ?? ediate data to acc 1 z ? c ? ac ? ov ? sc adc a ? [ ? ] add data me ? o ? y to acc with ca ?? y 1 z ? c ? ac ? ov ? sc adcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y 1 ? ote z ? c ? ac ? ov ? sc sub a ? x su ? t ? act i ?? ediate data f ? o ? the acc 1 z ? c ? ac ? ov ? sc ? cz sub a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc 1 z ? c ? ac ? ov ? sc ? cz subm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y 1 ? ote z ? c ? ac ? ov ? sc ? cz sbc a ? x su ? t ? act i ?? ediate data f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbc a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y 1 z ? c ? ac ? ov ? sc ? cz sbcm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y 1 ? ote z ? c ? ac ? ov ? sc ? cz daa [ ? ] deci ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 ? ote c logic operation a ? d a ? [ ? ] logical a ? d data me ? o ? y to acc 1 z or a ? [ ? ] logical or data me ? o ? y to acc 1 z xor a ? [ ? ] logical xor data me ? o ? y to acc 1 z a ? dm a ? [ ? ] logical a ? d acc to data me ? o ? y 1 ? ote z orm a ? [ ? ] logical or acc to data me ? o ? y 1 ? ote z xorm a ? [ ? ] logical xor acc to data me ? o ? y 1 ? ote z a ? d a ? x logical a ? d i ?? ediate data to acc 1 z or a ? x logical or i ?? ediate data to acc 1 z xor a ? x logical xor i ?? ediate data to acc 1 z cpl [ ? ] co ? ple ? ent data me ? o ? y 1 ? ote z cpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc 1 z increment & decrement i ? ca [ ? ] inc ? e ? ent data me ? o ? y with ? esult in acc 1 z i ? c [ ? ] inc ? e ? ent data me ? o ? y 1 ? ote z deca [ ? ] dec ? e ? ent data me ? o ? y with ? esult in acc 1 z dec [ ? ] dec ? e ? ent data me ? o ? y 1 ? ote z rotate rra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc 1 ? one rr [ ? ] rotate data me ? o ? y ? ight 1 ? ote ? one rrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc 1 c rrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y 1 ? ote c rla [ ? ] rotate data me ? o ? y left with ? esult in acc 1 ? one rl [ ? ] rotate data me ? o ? y left 1 ? ote ? one rlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc 1 c rlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y 1 ? ote c
rev. 1.60 150 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom mnemonic description cycles flag affected data move mov a ? [ ? ] move data me ? o ? y to acc 1 ? one mov [ ? ] ? a move acc to data me ? o ? y 1 ? ote ? one mov a ? x move i ?? ediate data to acc 1 ? one bit operation clr [ ? ].i clea ? ? it of data me ? o ? y 1 ? ote ? one set [ ? ].i set ? it of data me ? o ? y 1 ? ote ? one branch operation jmp add ? ju ? p unconditionally ? ? one sz [ ? ] skip if data me ? o ? y is ze ? o 1 ? ote ? one sza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc 1 ? ote ? one sz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o 1 ? ote ? one s ? z [ ? ] skip if data me ? o ? y is not ze ? o 1 ? ote ? one s ? z [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o 1 ? ote ? one siz [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o 1 ? ote ? one sdz [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o 1 ? ote ? one siza [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 ? ote ? one sdza [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o with ? esult in acc 1 ? ote ? one call add ? su ?? outine call ? ? one ret retu ? n f ? o ? su ?? outine ? ? one ret a ? x retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc ? ? one reti retu ? n f ? o ? inte ?? upt ? ? one table read operation tabrd [ ? ] read table (specifc page) to tblh and data memory ? ? ote ? one tabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y ? ? ote ? one itabrd [ ? ] increment table pointer tblp frst and read table to tblh and data memory ? ? ote ? one itabrdl [ ? ] increment table pointer tblp frst and read table (last page) to tblh and data me ? o ? y ? ? ote ? one miscellaneous ? op ? o ope ? ation 1 ? one clr [ ? ] clea ? data me ? o ? y 1 ? ote ? one set [ ? ] set data me ? o ? y 1 ? ote ? one clr wdt clea ? watchdog ti ? e ? 1 to ? pdf swap [ ? ] swap ni ?? les of data me ? o ? y 1 ? ote ? one swapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc 1 ? one halt ente ? powe ? down ? ode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt instruction the t o and pdf fags may be af fected by the execution status. the t o and pdf fags are cleared after the clr wdt instructions is executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.60 151 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom extended instruction set the extended instructions are used to support the full range address access for the data memory . when the accessed data memory is located in any data memory sections except sector 0, the extended instructi on can be used to access the data memory instead of using the indirect addressing access to improve the cpu frmware performance. mnemonic description cycles flag affected arithmetic ladd a ? [ ? ] add data me ? o ? y to acc ? z ? c ? ac ? ov ? sc laddm a ? [ ? ] add acc to data me ? o ? y ? ? ote z ? c ? ac ? ov ? sc ladc a ? [ ? ] add data me ? o ? y to acc with ca ?? y ? z ? c ? ac ? ov ? sc ladcm a ? [ ? ] add acc to data ? e ? o ? y with ca ?? y ? ? ote z ? c ? ac ? ov ? sc lsub a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc ? z ? c ? ac ? ov ? sc ? cz lsubm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y ? ? ote z ? c ? ac ? ov ? sc ? cz lsbc a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? z ? c ? ac ? ov ? sc ? cz lsbcm a ? [ ? ] su ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y ? ? ote z ? c ? ac ? ov ? sc ? cz ldaa [ ? ] deci ? al adjust acc fo ? addition with ? esult in data me ? o ? y ? ? ote c logic operation la ? d a ? [ ? ] logical a ? d data me ? o ? y to acc ? z lor a ? [ ? ] logical or data me ? o ? y to acc ? z lxor a ? [ ? ] logical xor data me ? o ? y to acc ? z la ? dm a ? [ ? ] logical a ? d acc to data me ? o ? y ? ? ote z lorm a ? [ ? ] logical or acc to data me ? o ? y ? ? ote z lxorm a ? [ ? ] logical xor acc to data me ? o ? y ? ? ote z lcpl [ ? ] co ? ple ? ent data me ? o ? y ? ? ote z lcpla [ ? ] co ? ple ? ent data me ? o ? y with ? esult in acc ? z increment & decrement li ? ca [ ? ] inc ? e ? ent data me ? o ? y with ? esult in acc ? z li ? c [ ? ] inc ? e ? ent data me ? o ? y ? ? ote z ldeca [ ? ] dec ? e ? ent data me ? o ? y with ? esult in acc ? z ldec [ ? ] dec ? e ? ent data me ? o ? y ? ? ote z rotate lrra [ ? ] rotate data me ? o ? y ? ight with ? esult in acc ? ? one lrr [ ? ] rotate data me ? o ? y ? ight ? ? ote ? one lrrca [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc ? c lrrc [ ? ] rotate data me ? o ? y ? ight th ? ough ca ?? y ? ? ote c lrla [ ? ] rotate data me ? o ? y left with ? esult in acc ? ? one lrl [ ? ] rotate data me ? o ? y left ? ? ote ? one lrlca [ ? ] rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc ? c lrlc [ ? ] rotate data me ? o ? y left th ? ough ca ?? y ? ? ote c data move lmov a ? [ ? ] move data me ? o ? y to acc ? ? one lmov [ ? ] ? a move acc to data me ? o ? y ? ? ote ? one bit operation lclr [ ? ].i clea ? ? it of data me ? o ? y ? ? ote ? one lset [ ? ].i set ? it of data me ? o ? y ? ? ote ? one
rev. 1.60 15 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom mnemonic description cycles flag affected branch lsz [ ? ] skip if data me ? o ? y is ze ? o ? ? ote ? one lsza [ ? ] skip if data me ? o ? y is ze ? o with data ? ove ? ent to acc ? ? ote ? one ls ? z [ ? ] skip if data me ? o ? y is not ze ? o ? ? ote ? one lsz [ ? ].i skip if ? it i of data me ? o ? y is ze ? o ? ? ote ? one ls ? z [ ? ].i skip if ? it i of data me ? o ? y is not ze ? o ? ? ote ? one lsiz [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o ? ? ote ? one lsdz [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o ? ? ote ? one lsiza [ ? ] skip if inc ? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? ? ote ? one lsdza [ ? ] skip if dec ? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? ? ote ? one table read ltabrd [ ? ] read ta ? le to tblh and data me ? o ? y 3 ? ote ? one ltabrdl [ ? ] read ta ? le (last page) to tblh and data me ? o ? y 3 ? ote ? one litabrd [ ? ] increment table pointer tblp frst and read table to tblh and data memory 3 ? ote ? one litabrdl [ ? ] increment table pointer tblp frst and read table (last page) to tblh and data me ? o ? y 3 ? ote ? one miscellaneous lclr [ ? ] clea ? data me ? o ? y ? ? ote ? one lset [ ? ] set data me ? o ? y ? ? ote ? one lswap [ ? ] swap ni ?? les of data me ? o ? y ? ? ote ? one lswapa [ ? ] swap ni ?? les of data me ? o ? y with ? esult in acc ? ? one note: 1. for these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. any extended instruction which changes the contents of the pcl register will also require three cycles for execution.
rev. 1.60 153 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c , s c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.60 154 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c
rev. 1.60 155 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none
rev. 1.60 156 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none
rev. 1.60 157 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory i s r otated r ight by 1 bit w ith bit 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c
rev. 1.60 158 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z sbc a, x subtract im mediate data f rom a cc w ith carry description the immediate da ta a nd t he c omplement o f t he c arry f ag a re s ubtracted f rom t he accumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is negative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is p ositive o r z ero, t he c f ag will be se t t o 1 . operation acc a cc - [ m] - c affected f ag(s) ov, z , ac , c , s c, cz sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none
rev. 1.60 159 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none snz [m] skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.60 160 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c , s c, c z swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.60 161 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tblp a nd t bhp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none itabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.60 16 ? ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom extended instruction defnition the extended instructions are used to directly access the data stored in any data memory sections. ladc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c ladcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c , s c ladd a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c , s c laddm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c , s c land a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z landm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z lclr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none lclr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none
rev. 1.60 163 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lcpl [m] complement d ata m emory description each b it o f t he s pecifed d ata m emory i s l ogically c omplemented ( 1s c omplement). b its which previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z lcpla [m] complement d ata m emory w ith r esult i n a cc description each b it o f t he s pecifed d ata m emory i s l ogically c omplemented ( 1s c omplement). b its which previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z ldaa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e affected b y t his i nstruction w hich i ndicates t hat i f t he original b cd su m i s g reater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c ldec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z ldeca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z linc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z linca [m] increment d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is incremented b y 1 . t he re sult is s tored in t he accumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.60 164 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lmov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none lmov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none lor a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z lorm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z lrl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none lrla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none lrlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c lrlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c
rev. 1.60 165 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lrr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none lrra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory i s r otated r ight by 1 bit w ith bit 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none lrrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c lrrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c lsbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z lsbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c , s c, c z
rev. 1.60 166 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lsdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none lsdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none lset [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none lset [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none lsiz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none lsiza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none lsnz [m].i skip i f d ata m emory i s no t 0 description if t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none
rev. 1.60 167 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lsnz [m] skip i f d ata m emory i s no t 0 description if t he c ontent o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s this re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a two c ycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] 0 affected f ag(s) none lsub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lsubm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c , s c, c z lswap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none lswapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none lsz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none lsza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none
rev. 1.60 168 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom lsz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none ltabrd [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none ltabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrd [m] increment ta ble p ointer l ow b yte fr st and r ead ta ble to t blh and d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he p rogram code addressed b y t he table p ointer ( tbhp and t blp) i s m oved to t he s pecifed d ata m emory and t he hi gh b yte moved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none litabrdl [m] increment t able p ointer l ow by te f rst a nd r ead t able (last p age) t o t blh a nd d ata m emory description increment ta ble p ointer l ow b yte, t blp, fr st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( tblp) i s m oved to t he s pecifed d ata m emory and the h igh by te mov ed t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none lxor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z lxorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z
rev. 1.60 169 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below . click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information
rev. 1.60 170 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom 44-pin lqfp (10mm10mm) (fp2.0mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.47 ? bsc b 0.394 bsc c 0.47 ? bsc d 0.394 bsc e 0.03 ? bsc f 0.01 ? 0.015 0.018 g 0.053 0.055 0.057 h 0.063 i 0.00 ? 0.006 j 0.018 0.0 ? 4 0.030 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 1 ? .00 bsc b 10.00 bsc c 1 ? .00 bsc d 10.00 bsc e 0.80 bsc f 0.30 0.37 0.45 g 1.35 1.40 1.45 h 1.60 i 0.05 0.15 j 0.45 0.60 0.75 k 0.09 0. ? 0 0 7
rev. 1.60 171 ? ove ?? e ? ??? ? 016 HT67F488/ht67f489 tinypower tm a/d flash mcu with lcd & eeprom copy ? ight ? ? 016 ? y holtek semico ? ductor i ? c. the info ?? ation appea ? ing in this data sheet is ? elieved to ? e accu ? ate at the ti ? e of pu ? lication. howeve ?? holtek assu ? es no ? esponsi ? ility a ? ising f ? o ? the use of the specifcations described. the applications mentioned herein are used solely fo ? the pu ? pose of illust ? ation and holtek ? akes no wa ?? anty o ? ? ep ? esentation that such applications will ? e suita ? le without fu ? the ? ? odification ? no ? ? eco ?? ends the use of its p ? oducts fo ? application that ? ay p ? esent a ? isk to hu ? an life due to ? alfunction o ? othe ? wise. holtek's p ? oducts a ? e not autho ? ized fo ? use as c ? itical co ? ponents in life suppo ? t devices o ? syste ? s. holtek ? ese ? ves the ? ight to alte ? its products without prior notifcation. for the most up-to-date information, please visit ou ? we ? site at http://www.holtek.co ? .tw.

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